From patchwork Mon Feb 4 22:25:37 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: kgene@kernel.org X-Patchwork-Id: 2095301 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id 77D2ADFE82 for ; Mon, 4 Feb 2013 22:26:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755887Ab3BDW0N (ORCPT ); Mon, 4 Feb 2013 17:26:13 -0500 Received: from mailout4.samsung.com ([203.254.224.34]:28875 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755014Ab3BDWZz (ORCPT ); Mon, 4 Feb 2013 17:25:55 -0500 Received: from epcpsbgm2.samsung.com (epcpsbgm2 [203.254.230.27]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MHP0032YVMYKT80@mailout4.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 05 Feb 2013 07:25:52 +0900 (KST) Received: from epcpsbgm2.samsung.com ( [203.254.230.51]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 08.A6.03880.07530115; Tue, 05 Feb 2013 07:25:52 +0900 (KST) X-AuditID: cbfee61b-b7fb06d000000f28-23-511035703003 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id E6.A6.03880.E6530115; Tue, 05 Feb 2013 07:25:50 +0900 (KST) Received: from visitor4lab ([105.128.18.157]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01 (7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MHP0047GVMZVP10@mmp1.samsung.com> for linux-samsung-soc@vger.kernel.org; Tue, 05 Feb 2013 07:25:50 +0900 (KST) From: kgene@kernel.org To: 'Santosh Shilimkar' , 'Benoit Cousson' Cc: 'Marc Zyngier' , 'Mark Rutland' , linux-samsung-soc@vger.kernel.org, 'Tony Lindgren' , devicetree-discuss@lists.ozlabs.org, rob.herring@calxeda.com, 'Grant Likely' , 'Thomas Abraham' , linux-arm-kernel@lists.infradead.org References: <1358818887-16870-1-git-send-email-kgene.kim@samsung.com> <20130122101554.GA18876@e106331-lin.cambridge.arm.com> <063f01cdf8ec$926cda30$b7468e90$@samsung.com> <20130123103614.GD32237@e106331-lin.cambridge.arm.com> <50FFC1B0.8000601@ti.com> <51012C4B.5080300@ti.com> <51013432.3080903@arm.com> <5108C9C9.4010409@ti.com> In-reply-to: <5108C9C9.4010409@ti.com> Subject: RE: [PATCH] ARM: dts: specify all the per-cpu interrupts of arch timer for exynos5440 Date: Mon, 04 Feb 2013 14:25:37 -0800 Message-id: <11ec01ce0326$90bcb590$b23620b0$@kernel.org> MIME-version: 1.0 Content-type: text/plain; charset=us-ascii Content-transfer-encoding: 7bit X-Mailer: Microsoft Outlook 14.0 Thread-index: AQMTjt4PWHFOh1YJzH1i6AX6HVGa9ADrkQcyAkqZhbMB6Ay6cgI5XIHZAmaSrRsCZC3N0wGK0pMelXHErEA= Content-language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrNIsWRmVeSWpSXmKPExsVy+t8zY90CU4FAg3uXLC1mnN/H5MDo8XmT XABjFJdNSmpOZllqkb5dAlfGr737mQou6lSc+TSJuYFxvVIXIyeHhICJxNq3R1kgbDGJC/fW s3UxcnEICSxjlPg5azsbTNHThoPsEIlFjBJ7r55jhXAWM0n86upk7mLk4GADap/6RBqkQVhA S2LhliawqSICkRIXvk1hBLGZBW4ySaw6awPRe4VJYvHhpWBFnAJqErN/HWaCaE6QWN62B6yB RUBV4ufD5WA1vAIWEj/mHGSFsAUlfky+xwIxVEti/c7jTBC2vMTmNW+ZIa5WkNhx9jUjxBEp Eq13N7JD1IhLTHrwEOwbCYF17BIdvR1QywQkvk0+xALyjISArMSmA1BzJCUOrrjBMoFRchaS 1bOQrJ6FZPUsJCsWMLKsYhRNLUguKE5KzzXSK07MLS7NS9dLzs/dxAiJOukdjKsaLA4xCnAw KvHw/rjMHyjEmlhWXJl7iFGCg1lJhPfjDaAQb0piZVVqUX58UWlOavEhxmSgYycyS4km5wMT Ql5JvKGxsYmZiamJuaWpuSlpwkrivIynngQICaQnlqRmp6YWpBbBbGHi4JRqYMz3OCvTPDM1 7aBDcWCwv5NBn6qtwstdp2tnsss901O5eeJE/9P3mryLOUInnjurxfG2I+gne5V0MbMMx6Ht p6KOf3F5wupdZd53OfOPcnOkU/nsA8YHyrnmnPnk/7jpxA9Fj0Vf4wLX/7rgUXw74fjqX/uX TNANeCEbxSVke+uzWtPn3CX8q5VYijMSDbWYi4oTAa4smpH+AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFKsWRmVeSWpSXmKPExsVy+t9jAd08U4FAg6fX9C1mnN/H5MDo8XmT XABjVAOjTUZqYkpqkUJqXnJ+SmZeuq2Sd3C8c7ypmYGhrqGlhbmSQl5ibqqtkotPgK5bZg7Q VCWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1GBmggYR1jxq+9+5kKLupUnPk0ibmB cb1SFyMnh4SAicTThoPsELaYxIV769m6GLk4hAQWMUrsvXqOFcJZzCTxq6uTuYuRg4MNqGrq E2mQBmEBLYmFW5pYQGwRgUiJC9+mMILYzAI3mSRWnbWB6L3CJLH48FKwIk4BNYnZvw4zQTQn SCxv2wPWwCKgKvHz4XKwGl4BC4kfcw6yQtiCEj8m32OBGKolsX7ncSYIW15i85q3zBBXK0js OPuaEeKIFInWuxvZIWrEJSY9eMg+gVF4FpJRs5CMmoVk1CwkLQsYWVYxiqYWJBcUJ6XnGukV J+YWl+al6yXn525iBMf0M+kdjKsaLA4xCnAwKvHw/rjMHyjEmlhWXJl7iFGCg1lJhPfjDaAQ b0piZVVqUX58UWlOavEhxmSgTycyS4km5wPTTV5JvKGxiZmRpZGZhZGJuTlpwkrivIynngQI CaQnlqRmp6YWpBbBbGHi4JRqYFT/8Wrqu5+xzRsu2taVzApvml7ZE8QddfylzvvQT8Jeh07G zPN33MLIvSl7Su7hhkXHpWYLHW60dLiy+NE7pVzmlgM9V46Hin6PnGngvyF4uxWTmY5c9Z/L uyce77w7py7C545rckjURIXJth9FmlOXNN7mffqFQ6hHr+G/pJXEQaOtu/NelyqxFGckGmox FxUnAgCax6h2LQMAAA== DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Santosh Shilimkar wrote: > > Benoit, > > On Thursday 24 January 2013 06:46 PM, Marc Zyngier wrote: > > Hi Benoit, > > > > On 24/01/13 12:42, Benoit Cousson wrote: > >> Hi Santosh, > >> > >> On 01/23/2013 11:55 AM, Santosh Shilimkar wrote: > >>> Looping Marc, Benoit > >>> > >>> On Wednesday 23 January 2013 04:06 PM, Mark Rutland wrote: > >>>> On Tue, Jan 22, 2013 at 10:05:18PM +0000, Kukjin Kim wrote: > >>>>> Mark Rutland wrote: > >>>>>> > >>>>> + devicetree-discuss, Grant Likely, Rob Herring and Tony Lindgren > >>>>> > >>>>>> On Tue, Jan 22, 2013 at 01:41:27AM +0000, Kukjin Kim wrote: > >>>>>>> From: Thomas Abraham > >>>>>>> > >>>>>>> Need to be changed requirements in the 'cpus' node for > exynos5440 > >>>>>>> to specify all the per-cpu interrupts of arch timer. > >>>>>> > >>>>>> The node(s) for the arch timer should not be in the cpus/cpu@N > nodes. > >>>>>> Instead, there should be one node (in the root of the tree). > >>>>>> > >>>>> Well, I don't think so. As per my understanding, the local timers are > >>>>> attached to every ARM cores (cpus) and it generates certain interrupt > >>>>> to the > >>>>> GIC. So the correct representation for this in device tree is to > >>>>> include the > >>>>> interrupts in the cpu nodes in dts file. Your comments refer to a > >>>>> limitation in the Linux kernel implementation of the arch_timer and it > >>>>> should not result in representing the hardware details incorrectly in > >>>>> the > >>>>> dts file. > >>>> > >>>> I disagree. The "correct representation" is whatever the devicetree > >>>> binding > >>>> documentation describes. It does not describe placing timer nodes in > >>>> the cpu > >>>> nodes. > >>>> > >>> This seems to be exact same topic what is getting discussed here [1] > >>> Technically DT is suppose to represent how the hardware is rather than > >>> how the bindings are done. > >>> > >>> But as Marc pointed out, the approach taken currently is to not > >>> duplicate the banked information. The thread [1] isn't concluded > >>> yet but looks like we might want to avoid duplicating the information > >>> considering, more of such duplication needs to follow. e.g gic i/f > >>> > >>> Am still waiting on what Benoit has to say ? > >> > >> I agree with you :-) > >> > >> I'm not sure the binding was properly done to reflect the HW accurately. > >> > >> A local timer for my point of view should be located in the cpu node > >> like a L1 cache. Or at least referenced in each cpu by a phandle. > >> > >> What was the rational to put it in the root? > > > > The rational was to follow what we already do for most (all?) banked > > resources. We already have TWD, GIC and PMU that have a root node, > > avoiding duplicated resources. I think consistency is an important thing > > to have. > > > > If we decide to move everything into CPU nodes and duplicate all the > > banked resources, fine. But that has impacts that reach far beyond the > > simple case of the timer. > > > > In particular, good luck with the GIC distributor interface, where the > > 32 first interrupts are per CPU. This would also mandate a redesign of > > the way we specify a PPI, as the CPU mask in the third field doesn't > > mean a thing anymore. > > > > If you insist on having a phandle to a timer node, fine by me. > > > Can you please comment on it so that we can conclude this thread ? > I would like to update my patches and hence the push. > Hmm...it's time to decide for now. Let me add timer node for ARM arch timer at this moment. Then if any change is required, will do it later. If any objection, let me know. If not, I will queue following patch for v3.9. Thanks. - Kukjin ---------8<------------------------------8<--------------------------------- - From: Kukjin Kim Subject: [PATCH] ARM: dts: re-organized cpu node for exynos5440 This patch adds timer node and re-organizes cpu node for exynos5440. Acked-by: Thomas Abraham Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5440.dtsi | 37 +++++++++++++++++-------------------- 1 file changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi index 1e7a2b0..5c5a699 100644 --- a/arch/arm/boot/dts/exynos5440.dtsi +++ b/arch/arm/boot/dts/exynos5440.dtsi @@ -24,40 +24,37 @@ }; cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 13 0xf08>; - clock-frequency = <1000000>; - }; + reg = <0>; }; cpu@1 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <1>; }; cpu@2 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <2>; }; cpu@3 { compatible = "arm,cortex-a15"; - timer { - compatible = "arm,armv7-timer"; - interrupts = <1 14 0xf08>; - clock-frequency = <1000000>; - }; + reg = <3>; }; }; + timer { + compatible = "arm,cortex-a15-timer", + "arm,armv7-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + clock-frequency = <50000000>; + }; + serial@B0000 { compatible = "samsung,exynos4210-uart"; reg = <0xB0000 0x1000>;