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[08/19] drm/i915: clean up plane bpp confusion

Message ID 1360755142-19145-9-git-send-email-daniel.vetter@ffwll.ch (mailing list archive)
State New, archived
Headers show

Commit Message

Daniel Vetter Feb. 13, 2013, 11:32 a.m. UTC 
- There is no 16bpc linear color format in our hw. gen4+ has a 16 bpc
  float layout, but we don't really support it.
- 10bpc is a gen4+ feature, fix up the support for it.
- Update_plane should never see a wrong fb bpp value, BUG in the
  corresponding cases.

v2: Rebase on top of Ville's plane pixel layout changes.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
---
 drivers/gpu/drm/i915/intel_display.c | 15 ++++++++-------
 1 file changed, 8 insertions(+), 7 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index d686b26..6f1b5cc 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2072,8 +2072,7 @@  static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 		dspcntr |= DISPPLANE_RGBX101010;
 		break;
 	default:
-		DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
-		return -EINVAL;
+		BUG();
 	}
 
 	if (INTEL_INFO(dev)->gen >= 4) {
@@ -2166,8 +2165,7 @@  static int ironlake_update_plane(struct drm_crtc *crtc,
 		dspcntr |= DISPPLANE_RGBX101010;
 		break;
 	default:
-		DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
-		return -EINVAL;
+		BUG();
 	}
 
 	if (obj->tiling_mode != I915_TILING_NONE)
@@ -7276,11 +7274,14 @@  pipe_config_set_bpp(struct drm_crtc *crtc,
 		bpp = 8*3;
 		break;
 	case 30:
+		if (INTEL_INFO(dev)->gen < 4) {
+			DRM_DEBUG_KMS("10 bpc not supported on gen2/3\n");
+			return -EINVAL;
+		}
+
 		bpp = 10*3;
 		break;
-	case 48:
-		bpp = 12*3;
-		break;
+	/* gen4+ supports 16 bpc floating point, too. */
 	default:
 		DRM_DEBUG_KMS("unsupported depth\n");
 		return -EINVAL;