diff mbox

drm/i915: Set i9xx sdvo clock limits according to specifications

Message ID 1360790422-6935-2-git-send-email-patrik.r.jakobsson@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Patrik Jakobsson Feb. 13, 2013, 9:20 p.m. UTC
The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
Since we do all calculations based on them being register values (which are
subtracted by 2) we need to specify them accordingly.

Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
---
 drivers/gpu/drm/i915/intel_display.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Chris Wilson Feb. 14, 2013, 8:50 p.m. UTC | #1
On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote:
> The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
> Since we do all calculations based on them being register values (which are
> subtracted by 2) we need to specify them accordingly.
> 
> Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
Daniel Vetter Feb. 14, 2013, 8:59 p.m. UTC | #2
On Thu, Feb 14, 2013 at 08:50:25PM +0000, Chris Wilson wrote:
> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote:
> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
> > Since we do all calculations based on them being register values (which are
> > subtracted by 2) we need to specify them accordingly.
> > 
> > Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
> 
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Queued both for -next with a cc: stable tag to increase the odds of
detecting bugs (or fixing some). Thanks for the patches.
-Daniel
> -Chris
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre
Dave Airlie Feb. 14, 2013, 9:45 p.m. UTC | #3
On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
> On Thu, Feb 14, 2013 at 08:50:25PM +0000, Chris Wilson wrote:
>> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote:
>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
>> > Since we do all calculations based on them being register values (which are
>> > subtracted by 2) we need to specify them accordingly.
>> >
>> > Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
>>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>
> Queued both for -next with a cc: stable tag to increase the odds of
> detecting bugs (or fixing some). Thanks for the patches.
> -Daniel

yeah no stable for this sorta thing, this could go horribly wrong, if
it fxies something stable it later.

stable isn't meant for testing patches that could break things.

Dave.
Daniel Vetter Feb. 14, 2013, 9:49 p.m. UTC | #4
On Thu, Feb 14, 2013 at 10:45 PM, Dave Airlie <airlied@gmail.com> wrote:
> On Fri, Feb 15, 2013 at 6:59 AM, Daniel Vetter <daniel@ffwll.ch> wrote:
>> On Thu, Feb 14, 2013 at 08:50:25PM +0000, Chris Wilson wrote:
>>> On Wed, Feb 13, 2013 at 10:20:22PM +0100, Patrik Jakobsson wrote:
>>> > The Intel PRM says the M1 and M2 divisors must be in the range of 10-20 and 5-9.
>>> > Since we do all calculations based on them being register values (which are
>>> > subtracted by 2) we need to specify them accordingly.
>>> >
>>> > Signed-off-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
>>>
>>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>>
>> Queued both for -next with a cc: stable tag to increase the odds of
>> detecting bugs (or fixing some). Thanks for the patches.
>> -Daniel
>
> yeah no stable for this sorta thing, this could go horribly wrong, if
> it fxies something stable it later.
>
> stable isn't meant for testing patches that could break things.

Ok, unstabled again. But wouldn't really have been the first time we'd
throw a revert to stable ;-)
-Daniel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4f6c594..458dfd9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -154,8 +154,8 @@  static const intel_limit_t intel_limits_i9xx_sdvo = {
 	.vco = { .min = 1400000, .max = 2800000 },
 	.n = { .min = 1, .max = 6 },
 	.m = { .min = 70, .max = 120 },
-	.m1 = { .min = 10, .max = 22 },
-	.m2 = { .min = 5, .max = 9 },
+	.m1 = { .min = 8, .max = 18 },
+	.m2 = { .min = 3, .max = 7 },
 	.p = { .min = 5, .max = 80 },
 	.p1 = { .min = 1, .max = 8 },
 	.p2 = { .dot_limit = 200000,