From patchwork Tue Feb 26 09:56:53 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inderpal Singh X-Patchwork-Id: 2184821 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork1.kernel.org (Postfix) with ESMTP id B23AD3FCF2 for ; Tue, 26 Feb 2013 09:57:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759759Ab3BZJ5H (ORCPT ); Tue, 26 Feb 2013 04:57:07 -0500 Received: from mail-pa0-f45.google.com ([209.85.220.45]:37678 "EHLO mail-pa0-f45.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759185Ab3BZJ5F (ORCPT ); Tue, 26 Feb 2013 04:57:05 -0500 Received: by mail-pa0-f45.google.com with SMTP id kl14so2350436pab.32 for ; Tue, 26 Feb 2013 01:57:05 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-received:from:to:cc:subject:date:message-id:x-mailer :x-gm-message-state; bh=fPegCYSojvrbK8iMzYTbkuDrPDtpxr5UkFYj34G+wP0=; b=fYogaVMiO96mSmCSVKIZbpUQY9bvqsSVASM30ftmU07xv0Q0Te0Q29KzlrtmV9PVxv IuNkYRNEoFBY3d/LgWyxW4t+bX7JXlAmpS90N8IQFR40WGsatnMFLPy6yfd93ePQ/dDg yvzYpqpf9n6Zw8fUjKOSt07YGP/rpp/FmFCSq7mq+O768eC+wb0VHbU+v6tb2p9NmREs tVKwssc6dfoH5LpBcmns49clOFjiBKawCc9xmiR4NohxWdINeVpfhJL57Ya4xGZdoQcy gY/SO4KKUQRRymH3Yu17GE9hfTcdTmrZ7i9+xf9KEDq94Wbvbry2MQTq3j5lyMOaGgKI 9tXA== X-Received: by 10.68.224.169 with SMTP id rd9mr22411957pbc.199.1361872625177; Tue, 26 Feb 2013 01:57:05 -0800 (PST) Received: from inder-ubuntu.sisodomain.com ([115.113.119.130]) by mx.google.com with ESMTPS id i6sm909833paw.19.2013.02.26.01.57.01 (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 26 Feb 2013 01:57:04 -0800 (PST) From: Inderpal Singh To: linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: kgene.kim@samsung.com, patches@linaro.org Subject: [PATCH v2] arm: plat-samsung: check processor type before cache restoration in resume Date: Tue, 26 Feb 2013 15:26:53 +0530 Message-Id: <1361872613-12040-1-git-send-email-inderpal.singh@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQmSGPOlsQQhd3O+SKmdC7iDCRfC/EHBIg2Jf8tboPtmswQMZmZ2EEelhUn2PKGVpg/VTP6o Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check the same before restoring the cache in resume. This is needed for single kernel image. Signed-off-by: Inderpal Singh --- changes in v2: - check processor midr instead of checking all soc ids as suggested by Kukjin arch/arm/mach-exynos/common.c | 4 ++++ arch/arm/plat-samsung/include/plat/pm.h | 1 + arch/arm/plat-samsung/s5p-sleep.S | 10 ++++++++++ 3 files changed, 15 insertions(+) diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c index c4b2071..5585325 100644 --- a/arch/arm/mach-exynos/common.c +++ b/arch/arm/mach-exynos/common.c @@ -31,6 +31,7 @@ #include #include #include +#include #include #include @@ -53,6 +54,7 @@ #include "common.h" #define L2_AUX_VAL 0x7C470001 #define L2_AUX_MASK 0xC200ffff +#define CPU_MASK 0xff0ffff0 static const char name_exynos4210[] = "EXYNOS4210"; static const char name_exynos4212[] = "EXYNOS4212"; @@ -716,6 +718,8 @@ static int __init exynos4_l2x0_cache_init(void) if (soc_is_exynos5250() || soc_is_exynos5440()) return 0; + cpu_midr = read_cpuid_id() & CPU_MASK; + ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK); if (!ret) { l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs); diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6fcade..532f5d7 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h @@ -184,3 +184,4 @@ extern void samsung_pm_save_gpios(void); extern void s3c_pm_save_core(void); extern void s3c_pm_restore_core(void); +extern unsigned long cpu_midr; diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dad..3b350d0 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,8 @@ #include #include +#define CPU_CORTEX_A9 0x410FC090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +53,11 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + adr r0, cpu_midr + ldr r1, [r0] + ldr r0, =CPU_CORTEX_A9 + cmp r1, r0 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE] @@ -77,4 +84,7 @@ ENDPROC(s3c_cpu_resume) .globl l2x0_regs_phys l2x0_regs_phys: .long 0 + .globl cpu_midr +cpu_midr: + .long 0 #endif