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[13/21] clk: samsung: exynos4: Add missing mout_sata on Exynos4210

Message ID 1364382178-25248-14-git-send-email-t.figa@samsung.com (mailing list archive)
State New, archived
Headers show

Commit Message

Tomasz Figa March 27, 2013, 11:02 a.m. UTC 
This patch adds missing mout_sata that is a parent of div_sata clock.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
---
 drivers/clk/samsung/clk-exynos4.c | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 0586421..959402f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -359,6 +359,7 @@  struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
 	MUX(none, "mout_mmc2", group1_p4210, SRC_FSYS, 8, 4),
 	MUX(none, "mout_mmc3", group1_p4210, SRC_FSYS, 12, 4),
 	MUX(none, "mout_mmc4", group1_p4210, SRC_FSYS, 16, 4),
+	MUX(none, "mout_sata", sclk_ampll_p4210, SRC_FSYS, 24, 1),
 	MUX(none, "mout_uart0", group1_p4210, SRC_PERIL0, 0, 4),
 	MUX(none, "mout_uart1", group1_p4210, SRC_PERIL0, 4, 4),
 	MUX(none, "mout_uart2", group1_p4210, SRC_PERIL0, 8, 4),