diff mbox

[v2] drm/i915: use lower aux clock divider on non-ULT HSW

Message ID 1365484260-3868-1-git-send-email-jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jani Nikula April 9, 2013, 5:11 a.m. UTC
Workaround to avoid intermittent aux channel failures, per spec change.

v2: Don't mess with cpu dp aux divider (Paulo Zanoni)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

Untested.
---
 drivers/gpu/drm/i915/intel_dp.c |    8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

Comments

Paulo Zanoni April 9, 2013, 2:49 p.m. UTC | #1
Hi

2013/4/9 Jani Nikula <jani.nikula@intel.com>:
> Workaround to avoid intermittent aux channel failures, per spec change.
>
> v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> ---
>
> Untested.
> ---
>  drivers/gpu/drm/i915/intel_dp.c |    8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 482b5e5..f8474d1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
>                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
>                 else
>                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> -       } else if (HAS_PCH_SPLIT(dev))
> +       } else  if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {

There's a space and a tab between "else" and "if", but I guess Daniel
will fix this :)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

> +               /* Workaround for non-ULT HSW */
> +               aux_clock_divider = 74;
> +       } else if (HAS_PCH_SPLIT(dev)) {
>                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> -       else
> +       } else {
>                 aux_clock_divider = intel_hrawclk(dev) / 2;
> +       }
>
>         if (IS_GEN6(dev))
>                 precharge = 3;
> --
> 1.7.10.4
>



--
Paulo Zanoni
Daniel Vetter April 9, 2013, 2:59 p.m. UTC | #2
On Tue, Apr 09, 2013 at 11:49:45AM -0300, Paulo Zanoni wrote:
> Hi
> 
> 2013/4/9 Jani Nikula <jani.nikula@intel.com>:
> > Workaround to avoid intermittent aux channel failures, per spec change.
> >
> > v2: Don't mess with cpu dp aux divider (Paulo Zanoni)
> >
> > Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >
> > ---
> >
> > Untested.
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c |    8 ++++++--
> >  1 file changed, 6 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index 482b5e5..f8474d1 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -353,10 +353,14 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> >                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
> >                 else
> >                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
> > -       } else if (HAS_PCH_SPLIT(dev))
> > +       } else  if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
> 
> There's a space and a tab between "else" and "if", but I guess Daniel
> will fix this :)

Done.

> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Queued for -next, thanks for the patch.
-Daniel
> 
> > +               /* Workaround for non-ULT HSW */
> > +               aux_clock_divider = 74;
> > +       } else if (HAS_PCH_SPLIT(dev)) {
> >                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
> > -       else
> > +       } else {
> >                 aux_clock_divider = intel_hrawclk(dev) / 2;
> > +       }
> >
> >         if (IS_GEN6(dev))
> >                 precharge = 3;
> > --
> > 1.7.10.4
> >
> 
> 
> 
> --
> Paulo Zanoni
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 482b5e5..f8474d1 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -353,10 +353,14 @@  intel_dp_aux_ch(struct intel_dp *intel_dp,
 			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 		else
 			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
-	} else if (HAS_PCH_SPLIT(dev))
+	} else 	if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
+		/* Workaround for non-ULT HSW */
+		aux_clock_divider = 74;
+	} else if (HAS_PCH_SPLIT(dev)) {
 		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
-	else
+	} else {
 		aux_clock_divider = intel_hrawclk(dev) / 2;
+	}
 
 	if (IS_GEN6(dev))
 		precharge = 3;