diff mbox

[5/7] drm/i915: clear FPGA_DBG_RM_NOCLAIM when capturing error state

Message ID 1366313746-3659-6-git-send-email-przanoni@gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Paulo Zanoni April 18, 2013, 7:35 p.m. UTC 
From: Paulo Zanoni <paulo.r.zanoni@intel.com>

In the error state function we read the registers without checking if
the power well is on, so after doing this we have to clear the
FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting
it and printing an error message.

The first version of this patch was checking for the power well state
and then avoiding reading registers that were off, but the reviewers
requested to just read the registers any way and then later clear the
FPGA_DBG_RM_NOCLAIM bit.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |    7 +++++++
 1 file changed, 7 insertions(+)

Comments

Lespiau, Damien April 19, 2013, 5:49 a.m. UTC | #1 
On Thu, Apr 18, 2013 at 04:35:44PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> In the error state function we read the registers without checking if
> the power well is on, so after doing this we have to clear the
> FPGA_DBG_RM_NOCLAIM bit to prevent the next I915_WRITE from detecting
> it and printing an error message.
> 
> The first version of this patch was checking for the power well state
> and then avoiding reading registers that were off, but the reviewers
> requested to just read the registers any way and then later clear the
> FPGA_DBG_RM_NOCLAIM bit.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 215f76c..43de5ef 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9585,6 +9585,13 @@  intel_display_capture_error_state(struct drm_device *dev)
 		error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
 	}
 
+	/* In the code above we read the registers without checking if the power
+	 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
+	 * prevent the next I915_WRITE from detecting it and printing an error
+	 * message. */
+	if (HAS_POWER_WELL(dev))
+		I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
+
 	return error;
 }