@@ -745,6 +745,25 @@ intel_dp_compute_config(struct intel_encoder *encoder,
/* Walk through all bpp values. Luckily they're all nicely spaced with 2
* bpc in between. */
bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
+
+ /*
+ * eDP panels are really fickle, try to enfore the bpp the firmware
+ * recomments. This means we'll up-dither 16bpp framebuffers on
+ * high-depth panels.
+ */
+ if (is_edp(intel_dp) && dev_priv->edp.bpp) {
+ DRM_DEBUG_KMS("forcing bpp for eDP panel to BIOS-provided %i\n",
+ dev_priv->edp.bpp);
+ /*
+ * But for added hilarity some of the 18bpp panels only work if
+ * we set up the pipe with enough bw for a 24bpp mode, since
+ * that's what the bios apparently does. So start the bw
+ * calculation with at least 24 bpp (down-dither is still
+ * possible).
+ */
+ bpp = max_t(int, dev_priv->edp.bpp, 24);
+ }
+
for (; bpp >= 6*3; bpp -= 2*3) {
mode_rate = intel_dp_link_required(target_clock, bpp);
@@ -795,11 +814,8 @@ found:
&pipe_config->dp_m_n);
/*
- * XXX: We have a strange regression where using the vbt edp bpp value
- * for the link bw computation results in black screens, the panel only
- * works when we do the computation at the usual 24bpp (but still
- * requires us to use 18bpp). Until that's fully debugged, stay
- * bug-for-bug compatible with the old code.
+ * Since we might have picked a too high bpp for the bw calculation,
+ * clamp it down again to make even the most fickle eDP panel happy.
*/
if (is_edp(intel_dp) && dev_priv->edp.bpp) {
DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",