From patchwork Thu Jun 6 11:01:16 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 2678931 Return-Path: X-Original-To: patchwork-linux-samsung-soc@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork2.kernel.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by patchwork2.kernel.org (Postfix) with ESMTP id F22EDDF23A for ; Thu, 6 Jun 2013 11:02:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932311Ab3FFLCj (ORCPT ); Thu, 6 Jun 2013 07:02:39 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:41823 "EHLO mail-pd0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932076Ab3FFLCi (ORCPT ); Thu, 6 Jun 2013 07:02:38 -0400 Received: by mail-pd0-f172.google.com with SMTP id t10so3206462pdi.17 for ; Thu, 06 Jun 2013 04:02:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=VCWH3XoeYc51xD+LLGekvNiMGeKlT7oOuvAUwsYgHgA=; b=GmZJMSOPucPasSbFQ5n42/MjkxGRVv0sPQg1bUSPO2jF9piCs2XZOQXkmknbdArH+c gRlvjc9ZcqigXf9XyhqMG0IbFo2A3TEWl2hFjyWCjDHNIsdlinXQeiW8pcZo+2ABuXUv HeJono9MSKEd5WGXSk2pAHPr2sHqB6NdWjVpYlNfH26RqLbLnBIlR0P+rL1RHNNlxYld ea7eJxIV2OPdA7gPwZeeEDc7N+i6X0XuZnpbfR+APSN3l2EvzfCF/5+BA3d6ySWxD0TJ wUb8qq+H3zE58xUqSxug7948dhzdn7TB6kQZThHLVlzdCcfcTpIBtWr49Vkp13di7G+G vhSQ== X-Received: by 10.66.5.196 with SMTP id u4mr38294554pau.79.1370516558204; Thu, 06 Jun 2013 04:02:38 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPSA id qh4sm77248213pac.8.2013.06.06.04.02.34 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 06 Jun 2013 04:02:37 -0700 (PDT) From: Chander Kashyap To: linux-arm-kernel@lists.infradead.org Cc: linux-samsung-soc@vger.kernel.org, linux-serial@vger.kernel.org, kgene.kim@samsung.com, t.figa@samsung.com, s.nawrocki@samsung.com, thomas.ab@samsung.com, Chander Kashyap Subject: [PATCH 02/13] ARM: Exynos: fix secondary cpu power control register address calculation Date: Thu, 6 Jun 2013 16:31:16 +0530 Message-Id: <1370516488-25860-2-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org> References: <1370516488-25860-1-git-send-email-chander.kashyap@linaro.org> X-Gm-Message-State: ALoCoQmZZeHgPGlzv8vmVh7hysKGGSMzuaKTqoB4yimLHnob0AZZ3TzgIgHA2jD3rO5iR7uLvjhI Sender: linux-samsung-soc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-samsung-soc@vger.kernel.org The CPU power control register address calculation for secondary CPUs is generalized by calculating the register address using secondary cpu logical number. Signed-off-by: Chander Kashyap --- arch/arm/mach-exynos/include/mach/regs-pmu.h | 6 ++++++ arch/arm/mach-exynos/platsmp.c | 10 +++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h index 3f30aa1..b77f72c 100644 --- a/arch/arm/mach-exynos/include/mach/regs-pmu.h +++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h @@ -125,11 +125,17 @@ #define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0) #define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000) +#define S5P_ARM_CORE0_STATUS S5P_PMUREG(0x2004) #define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008) #define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080) #define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084) #define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088) +#define S5P_ARM_CORE_CONFIGURATION(_nr) \ + (S5P_ARM_CORE0_CONFIGURATION + (_nr) * 0x80) +#define S5P_ARM_CORE_STATUS(_nr) \ + (S5P_ARM_CORE0_STATUS + (_nr) * 0x80) + #define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408) #define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48) #define S5P_CAM_OPTION S5P_PMUREG(0x3C08) diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index d9c6d0a..1a4e4e5 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c @@ -109,14 +109,14 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct */ write_pen_release(phys_cpu); - if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) { + if (!(__raw_readl(S5P_ARM_CORE_STATUS(cpu)) & S5P_CORE_LOCAL_PWR_EN)) { __raw_writel(S5P_CORE_LOCAL_PWR_EN, - S5P_ARM_CORE1_CONFIGURATION); + S5P_ARM_CORE_CONFIGURATION(cpu)); timeout = 10; - /* wait max 10 ms until cpu1 is on */ - while ((__raw_readl(S5P_ARM_CORE1_STATUS) + /* wait max 10 ms until secondary cpu is on */ + while ((__raw_readl(S5P_ARM_CORE_STATUS(cpu)) & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) { if (timeout-- == 0) break; @@ -125,7 +125,7 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct } if (timeout == 0) { - printk(KERN_ERR "cpu1 power enable failed"); + pr_err("secondary cpu power enable failed\n"); spin_unlock(&boot_lock); return -ETIMEDOUT; }