b/drivers/gpu/drm/radeon/cypress_dpm.c
@@ -2169,6 +2169,8 @@ bool cypress_dpm_vblank_too_short(struct radeon_device
*rdev)
/* we never hit the non-gddr5 limit so disable it */
u32 switch_limit = pi->mem_gddr5 ? 450 : 0;
+ DRM_ERROR("vblank_time: %d switch_limit: %d", vblank_time,
switch_limit);
+
if (vblank_time < switch_limit)
return true;
else
b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -648,10 +648,15 @@ static struct radeon_ps
*radeon_dpm_pick_power_state(struct radeon_device *rdev,
/* check if the vblank period is too short to adjust the mclk */
if (single_display && rdev->asic->dpm.vblank_too_short) {
- if (radeon_dpm_vblank_too_short(rdev))
+ if (radeon_dpm_vblank_too_short(rdev)) {
+ DRM_ERROR("vblank too short\n");
single_display = false;
+ }
}
+ DRM_ERROR("single display = %d crtcs: %d", single_display,
+ rdev->pm.dpm.new_active_crtc_count);
+
/* certain older asics have a separare 3D performance state,
* so try that first if the user selected performance