| Message ID | 1378328120-1088-2-git-send-email-benjamin.widawsky@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Wed, Sep 04, 2013 at 01:55:20PM -0700, Ben Widawsky wrote: > Haswell changed the log registers to be WO, so we can no longer read > them to determine the programming (which sucks, see later note). For > now, simply use the cached value, and hope HW doesn't screw us over. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441 > Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Tested-by: shui yangwei <yangweix.shui@intel.com> > --- > > Notes: > I'll be able to parity tester feature shortly, so hopefully the current gap > will be filled. > > Also coming up will be support for the 2nd L3 slice. > > drivers/gpu/drm/i915/i915_sysfs.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c > index 8feb5f0..f71efbc 100644 > --- a/drivers/gpu/drm/i915/i915_sysfs.c > +++ b/drivers/gpu/drm/i915/i915_sysfs.c > @@ -129,6 +129,19 @@ i915_l3_read(struct file *filp, struct kobject *kobj, > if (ret) > return ret; > > + if (IS_HASWELL(drm_dev)) { > + int last = min_t(int, GEN7_L3LOG_SIZE, count + offset); > + if ((!dev_priv->l3_parity.remap_info)) > + memset(buf + offset, 0, last - offset); > + else > + memcpy(buf + offset, > + dev_priv->l3_parity.remap_info + (offset/4), > + last - offset); > + > + i = last; > + goto out; > + } > + > misccpctl = I915_READ(GEN7_MISCCPCTL); > I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); > > @@ -137,6 +150,7 @@ i915_l3_read(struct file *filp, struct kobject *kobj, > > I915_WRITE(GEN7_MISCCPCTL, misccpctl); > > +out: > mutex_unlock(&drm_dev->struct_mutex); > > return i - offset; > -- > 1.8.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c index 8feb5f0..f71efbc 100644 --- a/drivers/gpu/drm/i915/i915_sysfs.c +++ b/drivers/gpu/drm/i915/i915_sysfs.c @@ -129,6 +129,19 @@ i915_l3_read(struct file *filp, struct kobject *kobj, if (ret) return ret; + if (IS_HASWELL(drm_dev)) { + int last = min_t(int, GEN7_L3LOG_SIZE, count + offset); + if ((!dev_priv->l3_parity.remap_info)) + memset(buf + offset, 0, last - offset); + else + memcpy(buf + offset, + dev_priv->l3_parity.remap_info + (offset/4), + last - offset); + + i = last; + goto out; + } + misccpctl = I915_READ(GEN7_MISCCPCTL); I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); @@ -137,6 +150,7 @@ i915_l3_read(struct file *filp, struct kobject *kobj, I915_WRITE(GEN7_MISCCPCTL, misccpctl); +out: mutex_unlock(&drm_dev->struct_mutex); return i - offset;
Haswell changed the log registers to be WO, so we can no longer read them to determine the programming (which sucks, see later note). For now, simply use the cached value, and hope HW doesn't screw us over. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=57441 Signed-off-by: Ben Widawsky <ben@bwidawsk.net> --- Notes: I'll be able to parity tester feature shortly, so hopefully the current gap will be filled. Also coming up will be support for the 2nd L3 slice. drivers/gpu/drm/i915/i915_sysfs.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)