diff mbox

[3/3] drm/radeon/cik: Program pipe configuration for 1D tiling modes as well

Message ID 1379511582-8950-3-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer Sept. 18, 2013, 1:39 p.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---

Not sure this is necessary, but AFAICT the pipe configuration applies to
1D tiling modes as well.

 drivers/gpu/drm/radeon/cik.c | 48 +++++++++++++++++++++++++++++---------------
 1 file changed, 32 insertions(+), 16 deletions(-)

Comments

Alex Deucher Sept. 18, 2013, 1:56 p.m. UTC | #1 
On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
> ---
>
> Not sure this is necessary, but AFAICT the pipe configuration applies to
> 1D tiling modes as well.

I don't think pipe config applies to 1D modes since they are fixed
size across asics.

>
>  drivers/gpu/drm/radeon/cik.c | 48 +++++++++++++++++++++++++++++---------------
>  1 file changed, 32 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index 8feaf51..35d8247 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -1788,7 +1788,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 5:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
>                                 break;
>                         case 6:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -1808,7 +1809,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 9:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
>                                 break;
>                         case 10:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -1830,7 +1832,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 13:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
>                                 break;
>                         case 14:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -1852,7 +1855,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 27:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
>                                 break;
>                         case 28:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2007,7 +2011,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 5:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16);
>                                         break;
>                                 case 6:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -2027,7 +2032,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 9:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16);
>                                         break;
>                                 case 10:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2049,7 +2055,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 13:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16);
>                                         break;
>                                 case 14:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2071,7 +2078,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 27:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_16x16);
>                                         break;
>                                 case 28:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -2133,7 +2141,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 5:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16);
>                                         break;
>                                 case 6:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -2153,7 +2162,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 9:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16);
>                                         break;
>                                 case 10:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2175,7 +2185,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 13:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16);
>                                         break;
>                                 case 14:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2197,7 +2208,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                         break;
>                                 case 27:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> +                                                        MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
> +                                                        PIPE_CONFIG(ADDR_SURF_P4_8x16);
>                                         break;
>                                 case 28:
>                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -2352,7 +2364,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 5:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2);
>                                 break;
>                         case 6:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> @@ -2371,7 +2384,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 9:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2);
>                                 break;
>                         case 10:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2393,7 +2407,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 13:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2);
>                                 break;
>                         case 14:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> @@ -2415,7 +2430,8 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
>                                 break;
>                         case 27:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> -                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> +                                                MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
> +                                                PIPE_CONFIG(ADDR_SURF_P2);
>                                 break;
>                         case 28:
>                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> --
> 1.8.4.rc3
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
Michel Dänzer Sept. 18, 2013, 3:55 p.m. UTC | #2 
On Mit, 2013-09-18 at 09:56 -0400, Alex Deucher wrote:
> On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote:
> > From: Michel Dänzer <michel.daenzer@amd.com>
> >
> > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
> > ---
> >
> > Not sure this is necessary, but AFAICT the pipe configuration applies to
> > 1D tiling modes as well.
> 
> I don't think pipe config applies to 1D modes since they are fixed
> size across asics.

Makes sense. I noticed that we're setting pipe config for 1D tiling
modes on SI as well, and the documentation I saw didn't explicitly say
that it only applies to 2D tiling.

Maybe we should remove the setting of pipe config and friends for 1D
tiling modes on SI instead?
Alex Deucher Sept. 18, 2013, 4 p.m. UTC | #3 
On Wed, Sep 18, 2013 at 11:55 AM, Michel Dänzer <michel@daenzer.net> wrote:
> On Mit, 2013-09-18 at 09:56 -0400, Alex Deucher wrote:
>> On Wed, Sep 18, 2013 at 9:39 AM, Michel Dänzer <michel@daenzer.net> wrote:
>> > From: Michel Dänzer <michel.daenzer@amd.com>
>> >
>> > Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
>> > ---
>> >
>> > Not sure this is necessary, but AFAICT the pipe configuration applies to
>> > 1D tiling modes as well.
>>
>> I don't think pipe config applies to 1D modes since they are fixed
>> size across asics.
>
> Makes sense. I noticed that we're setting pipe config for 1D tiling
> modes on SI as well, and the documentation I saw didn't explicitly say
> that it only applies to 2D tiling.
>
> Maybe we should remove the setting of pipe config and friends for 1D
> tiling modes on SI instead?
>

I suppose we should try and double check.  The tiling settings
spreadsheets sets the fields for SI, but no CIK, but I don't think the
hw actually needs it.

Alex

>
> --
> Earthling Michel Dänzer           |                   http://www.amd.com
> Libre software enthusiast         |          Debian, X and DRI developer
>
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 8feaf51..35d8247 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -1788,7 +1788,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 5:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
 				break;
 			case 6:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -1808,7 +1809,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 9:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
 				break;
 			case 10:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -1830,7 +1832,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 13:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
 				break;
 			case 14:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -1852,7 +1855,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 27:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16);
 				break;
 			case 28:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2007,7 +2011,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 5:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16);
 					break;
 				case 6:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -2027,7 +2032,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 9:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16);
 					break;
 				case 10:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2049,7 +2055,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 13:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16);
 					break;
 				case 14:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2071,7 +2078,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 27:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_16x16);
 					break;
 				case 28:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -2133,7 +2141,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 5:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 					break;
 				case 6:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -2153,7 +2162,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 9:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 					break;
 				case 10:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2175,7 +2185,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 13:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 					break;
 				case 14:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2197,7 +2208,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 					break;
 				case 27:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+							 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
+							 PIPE_CONFIG(ADDR_SURF_P4_8x16);
 					break;
 				case 28:
 					gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -2352,7 +2364,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 5:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P2);
 				break;
 			case 6:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
@@ -2371,7 +2384,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 9:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P2);
 				break;
 			case 10:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2393,7 +2407,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 13:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P2);
 				break;
 			case 14:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
@@ -2415,7 +2430,8 @@  static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 				break;
 			case 27:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+						 MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING)) |
+						 PIPE_CONFIG(ADDR_SURF_P2);
 				break;
 			case 28:
 				gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |