[OPW,kernel] subject:[PATCH] /Staging/cxt1e1 : Fixes a coding style issue of incorrect brace placement
diff mbox

Message ID 1381162488-7468-1-git-send-email-archanakumari959@gmail.com
State Changes Requested
Headers show

Commit Message

Archana kumari Oct. 7, 2013, 4:14 p.m. UTC
this patch Fixes error "This open brace { should be on the
above line" detected via checkpatch.pl.

Signed-off-by: archana kumari <archanakumari959@gmail.com>
---
---
 drivers/staging/cxt1e1/comet.c | 24 ++++++++++++------------
 drivers/staging/cxt1e1/comet.h |  7 ++++---
 2 files changed, 16 insertions(+), 15 deletions(-)

Comments

Josh Triplett Oct. 7, 2013, 4:29 p.m. UTC | #1
Your subject doesn't quite work; you have:

[PATCH] subject:[PATCH] /Staging/cxt1e1 : Fixes a coding style issue of incorrect brace placement

You don't want the "subject:[PATCH]" there, and the prefix should look
like "staging: cxt1e1: ", like this:

[PATCH] staging: cxt1e1: Fixes a coding style issue of incorrect brace placement

On Mon, Oct 07, 2013 at 09:44:48PM +0530, Archana kumari wrote:
> this patch Fixes error "This open brace { should be on the
> above line" detected via checkpatch.pl.
> 
> Signed-off-by: archana kumari <archanakumari959@gmail.com>
> ---
>  drivers/staging/cxt1e1/comet.c | 24 ++++++++++++------------
>  drivers/staging/cxt1e1/comet.h |  7 ++++---
>  2 files changed, 16 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
> index d71aea5..80ee0b8 100644
> --- a/drivers/staging/cxt1e1/comet.c
> +++ b/drivers/staging/cxt1e1/comet.c
> @@ -145,8 +145,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
>      /* Enable 8 out of 10 validation */
>  	 /* t1RBOC enable(BOC:BitOriented Code) */
>  	pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
> -	if (isT1mode)
> -	{
> +	if (isT1mode) {
> +	

You don't need to leave a blank line here, and you definitely shouldn't
leave trailing whitespace.  (Likewise for the remaining changes in this
patch.)

> --- a/drivers/staging/cxt1e1/comet.h
> +++ b/drivers/staging/cxt1e1/comet.h
[...]
> @@ -122,7 +122,7 @@ VINT32 ibcd_deact;       /* 4F  IBCD Deactivate Code */
>  VINT32 sigx_cfg;         /* 50  SIGX Cfg/Change of Signaling State */
>  VINT32 sigx_acc_cos;     /* 51  SIGX uP Access Sts/Change of Signaling State */
>  VINT32 sigx_iac_cos;     /* 52  SIGX Channel Indirect
> -                              * Addr/Ctl/Change of Signaling State */
> +	                              * Addr/Ctl/Change of Signaling State */
>  VINT32 sigx_idb_cos;     /* 53  SIGX Channel Indirect Data
>                                * Buffer/Change of Signaling State */
>  

This looks like an unrelated change in the same patch.

> @@ -236,6 +236,7 @@ VINT32 __resAF;          /* AF     Reserved */
>  VINT32 tdpr2_cfg;        /* B0  TDPR #2 Cfg */
>  VINT32 tdpr2_utl;        /* B1  TDPR #2 Upper TX Threshold */
>  VINT32 tdpr2_ltl;        /* B2  TDPR #2 Lower TX Threshold */
> +
>  VINT32 tdpr2_ien;        /* B3  TDPR #2 Intr Enable */
>  VINT32 tdpr2_ists;       /* B4  TDPR #2 Intr Sts/UDR Clear */
>  VINT32 tdpr2_data;       /* B5  TDPR #2 TX Data */

This looks like an unrelated change in the same patch.

- Josh Triplett
Archana kumari Oct. 7, 2013, 4:58 p.m. UTC | #2
thanks Josh Triplett for your feedback
should i update this patch to fix your errors or try to be careful in my 
next patch?

On Monday, October 7, 2013 9:44:48 PM UTC+5:30, Archana Kumari wrote:
>
> this patch Fixes error "This open brace { should be on the 
> above line" detected via checkpatch.pl. 
>
> Signed-off-by: archana kumari <archanakumari959@gmail.com> 
> --- 
> --- 
>  drivers/staging/cxt1e1/comet.c | 24 ++++++++++++------------ 
>  drivers/staging/cxt1e1/comet.h |  7 ++++--- 
>  2 files changed, 16 insertions(+), 15 deletions(-) 
>
> diff --git a/drivers/staging/cxt1e1/comet.c 
> b/drivers/staging/cxt1e1/comet.c 
> index d71aea5..80ee0b8 100644 
> --- a/drivers/staging/cxt1e1/comet.c 
> +++ b/drivers/staging/cxt1e1/comet.c 
> @@ -145,8 +145,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>      /* Enable 8 out of 10 validation */ 
>           /* t1RBOC enable(BOC:BitOriented Code) */ 
>          pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00); 
> -        if (isT1mode) 
> -        { 
> +        if (isT1mode) { 
> +         
>   
>          /* IBCD cfg: aka Inband Code Detection ** loopback code length 
> set to */ 
>                  /* 6 bit down, 5 bit up (assert) */ 
> @@ -161,8 +161,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>      /* 60: t1 ALMI cfg */ 
>      /* Configure Line Coding */ 
>   
> -        switch (port_mode) 
> -        { 
> +        switch (port_mode) { 
> +         
>          /* 1 - T1 B8ZS */ 
>          case CFG_FRAME_SF: 
>                  pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); 
> @@ -288,8 +288,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>   
>      /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */ 
>      /* note "rate bits can only be set once after reset" */ 
> -        if (clockmaster) 
> -                { 
> +        if (clockmaster) { 
> +                 
>                  /* CMODE == clockMode, 0=clock master (so all 3 others 
> should be slave) */ 
>                  /* rate = 1.544 Mb/s */ 
>                  if (isT1mode) 
> @@ -304,8 +304,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>   
>                  /* Master Mode i.e.FPMODE=0 (@0x20) */ 
>                  pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00); 
> -                if ((moreParams & CFG_CLK_PORT_MASK) == 
> CFG_CLK_PORT_INTERNAL) 
> -                        { 
> +                if ((moreParams & CFG_CLK_PORT_MASK) == 
> CFG_CLK_PORT_INTERNAL) { 
> +                         
>                          if (cxt1e1_log_level >= LOG_SBEBUG12) 
>                                  pr_info(">> %s: clockmaster internal 
> clock\n", __func__); 
>                          /* internal oscillator */ 
> @@ -424,8 +424,8 @@ WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, 
>  { 
>          u_int32_t sample, unit; 
>   
> -        for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) 
> -                { 
> +        for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) { 
> +                 
>                  for (unit = 0; unit < COMET_NUM_UNITS; unit++) 
>                          WrtXmtWaveform(ci, comet, sample, unit, 
> table[sample][unit]); 
>                  } 
> @@ -556,8 +556,8 @@ SetCometOps(comet_t *comet) 
>  { 
>          volatile u_int8_t rd_value; 
>   
> -        if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) 
> -        { 
> +        if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) { 
> +         
>                  /* read the BRIF Configuration */ 
>                  rd_value = (u_int8_t) pci_read_32((u_int32_t *) 
> &comet->brif_cfg); 
>                  rd_value &= ~0x20; 
> diff --git a/drivers/staging/cxt1e1/comet.h 
> b/drivers/staging/cxt1e1/comet.h 
> index c9ae538..4025bbc 100644 
> --- a/drivers/staging/cxt1e1/comet.h 
> +++ b/drivers/staging/cxt1e1/comet.h 
> @@ -25,8 +25,8 @@ 
>   
>  #define VINT32  volatile u_int32_t 
>   
> -struct s_comet_reg 
> -{ 
> +struct s_comet_reg { 
> + 
>  VINT32 gbl_cfg;      /* 00  Global Cfg */ 
>  VINT32 clkmon;       /* 01  Clk Monitor */ 
>  VINT32 rx_opt;       /* 02  RX Options */ 
> @@ -122,7 +122,7 @@ VINT32 ibcd_deact;       /* 4F  IBCD Deactivate Code 
> */ 
>  VINT32 sigx_cfg;         /* 50  SIGX Cfg/Change of Signaling State */ 
>  VINT32 sigx_acc_cos;     /* 51  SIGX uP Access Sts/Change of Signaling 
> State */ 
>  VINT32 sigx_iac_cos;     /* 52  SIGX Channel Indirect 
> -                              * Addr/Ctl/Change of Signaling State */ 
> +                                      * Addr/Ctl/Change of Signaling 
> State */ 
>  VINT32 sigx_idb_cos;     /* 53  SIGX Channel Indirect Data 
>                                * Buffer/Change of Signaling State */ 
>   
> @@ -236,6 +236,7 @@ VINT32 __resAF;          /* AF     Reserved */ 
>  VINT32 tdpr2_cfg;        /* B0  TDPR #2 Cfg */ 
>  VINT32 tdpr2_utl;        /* B1  TDPR #2 Upper TX Threshold */ 
>  VINT32 tdpr2_ltl;        /* B2  TDPR #2 Lower TX Threshold */ 
> + 
>  VINT32 tdpr2_ien;        /* B3  TDPR #2 Intr Enable */ 
>  VINT32 tdpr2_ists;       /* B4  TDPR #2 Intr Sts/UDR Clear */ 
>  VINT32 tdpr2_data;       /* B5  TDPR #2 TX Data */ 
> -- 
> 1.8.1.2 
>
>
Josh Triplett Oct. 7, 2013, 5:26 p.m. UTC | #3
On Mon, Oct 07, 2013 at 09:58:02AM -0700, Archana Kumari wrote:
> thanks Josh Triplett for your feedback
> should i update this patch to fix your errors or try to be careful in my 
> next patch?

Please do go ahead and update this patch, and send a PATCHv2 to the
list.

- Josh Triplett
Archana kumari Oct. 7, 2013, 6:07 p.m. UTC | #4
okay Josh Triplett.
 I am not able to update the patch by using 

git format-patch --subject-prefix="PATCH v2"
but its resulting in error. 
anyone pleae help me out with this.
thanks.




On Monday, October 7, 2013 9:44:48 PM UTC+5:30, Archana Kumari wrote:
>
> this patch Fixes error "This open brace { should be on the 
> above line" detected via checkpatch.pl. 
>
> Signed-off-by: archana kumari <archanakumari959@gmail.com> 
> --- 
> --- 
>  drivers/staging/cxt1e1/comet.c | 24 ++++++++++++------------ 
>  drivers/staging/cxt1e1/comet.h |  7 ++++--- 
>  2 files changed, 16 insertions(+), 15 deletions(-) 
>
> diff --git a/drivers/staging/cxt1e1/comet.c 
> b/drivers/staging/cxt1e1/comet.c 
> index d71aea5..80ee0b8 100644 
> --- a/drivers/staging/cxt1e1/comet.c 
> +++ b/drivers/staging/cxt1e1/comet.c 
> @@ -145,8 +145,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>      /* Enable 8 out of 10 validation */ 
>           /* t1RBOC enable(BOC:BitOriented Code) */ 
>          pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00); 
> -        if (isT1mode) 
> -        { 
> +        if (isT1mode) { 
> +         
>   
>          /* IBCD cfg: aka Inband Code Detection ** loopback code length 
> set to */ 
>                  /* 6 bit down, 5 bit up (assert) */ 
> @@ -161,8 +161,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>      /* 60: t1 ALMI cfg */ 
>      /* Configure Line Coding */ 
>   
> -        switch (port_mode) 
> -        { 
> +        switch (port_mode) { 
> +         
>          /* 1 - T1 B8ZS */ 
>          case CFG_FRAME_SF: 
>                  pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0); 
> @@ -288,8 +288,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>   
>      /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */ 
>      /* note "rate bits can only be set once after reset" */ 
> -        if (clockmaster) 
> -                { 
> +        if (clockmaster) { 
> +                 
>                  /* CMODE == clockMode, 0=clock master (so all 3 others 
> should be slave) */ 
>                  /* rate = 1.544 Mb/s */ 
>                  if (isT1mode) 
> @@ -304,8 +304,8 @@ void init_comet(void *ci, comet_t *comet, u_int32_t 
> port_mode, int clockmaster, 
>   
>                  /* Master Mode i.e.FPMODE=0 (@0x20) */ 
>                  pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00); 
> -                if ((moreParams & CFG_CLK_PORT_MASK) == 
> CFG_CLK_PORT_INTERNAL) 
> -                        { 
> +                if ((moreParams & CFG_CLK_PORT_MASK) == 
> CFG_CLK_PORT_INTERNAL) { 
> +                         
>                          if (cxt1e1_log_level >= LOG_SBEBUG12) 
>                                  pr_info(">> %s: clockmaster internal 
> clock\n", __func__); 
>                          /* internal oscillator */ 
> @@ -424,8 +424,8 @@ WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, 
>  { 
>          u_int32_t sample, unit; 
>   
> -        for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) 
> -                { 
> +        for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) { 
> +                 
>                  for (unit = 0; unit < COMET_NUM_UNITS; unit++) 
>                          WrtXmtWaveform(ci, comet, sample, unit, 
> table[sample][unit]); 
>                  } 
> @@ -556,8 +556,8 @@ SetCometOps(comet_t *comet) 
>  { 
>          volatile u_int8_t rd_value; 
>   
> -        if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) 
> -        { 
> +        if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) { 
> +         
>                  /* read the BRIF Configuration */ 
>                  rd_value = (u_int8_t) pci_read_32((u_int32_t *) 
> &comet->brif_cfg); 
>                  rd_value &= ~0x20; 
> diff --git a/drivers/staging/cxt1e1/comet.h 
> b/drivers/staging/cxt1e1/comet.h 
> index c9ae538..4025bbc 100644 
> --- a/drivers/staging/cxt1e1/comet.h 
> +++ b/drivers/staging/cxt1e1/comet.h 
> @@ -25,8 +25,8 @@ 
>   
>  #define VINT32  volatile u_int32_t 
>   
> -struct s_comet_reg 
> -{ 
> +struct s_comet_reg { 
> + 
>  VINT32 gbl_cfg;      /* 00  Global Cfg */ 
>  VINT32 clkmon;       /* 01  Clk Monitor */ 
>  VINT32 rx_opt;       /* 02  RX Options */ 
> @@ -122,7 +122,7 @@ VINT32 ibcd_deact;       /* 4F  IBCD Deactivate Code 
> */ 
>  VINT32 sigx_cfg;         /* 50  SIGX Cfg/Change of Signaling State */ 
>  VINT32 sigx_acc_cos;     /* 51  SIGX uP Access Sts/Change of Signaling 
> State */ 
>  VINT32 sigx_iac_cos;     /* 52  SIGX Channel Indirect 
> -                              * Addr/Ctl/Change of Signaling State */ 
> +                                      * Addr/Ctl/Change of Signaling 
> State */ 
>  VINT32 sigx_idb_cos;     /* 53  SIGX Channel Indirect Data 
>                                * Buffer/Change of Signaling State */ 
>   
> @@ -236,6 +236,7 @@ VINT32 __resAF;          /* AF     Reserved */ 
>  VINT32 tdpr2_cfg;        /* B0  TDPR #2 Cfg */ 
>  VINT32 tdpr2_utl;        /* B1  TDPR #2 Upper TX Threshold */ 
>  VINT32 tdpr2_ltl;        /* B2  TDPR #2 Lower TX Threshold */ 
> + 
>  VINT32 tdpr2_ien;        /* B3  TDPR #2 Intr Enable */ 
>  VINT32 tdpr2_ists;       /* B4  TDPR #2 Intr Sts/UDR Clear */ 
>  VINT32 tdpr2_data;       /* B5  TDPR #2 TX Data */ 
> -- 
> 1.8.1.2 
>
>

Patch
diff mbox

diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
index d71aea5..80ee0b8 100644
--- a/drivers/staging/cxt1e1/comet.c
+++ b/drivers/staging/cxt1e1/comet.c
@@ -145,8 +145,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
     /* Enable 8 out of 10 validation */
 	 /* t1RBOC enable(BOC:BitOriented Code) */
 	pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
-	if (isT1mode)
-	{
+	if (isT1mode) {
+	
 
 	/* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
 		/* 6 bit down, 5 bit up (assert) */
@@ -161,8 +161,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
     /* 60: t1 ALMI cfg */
     /* Configure Line Coding */
 
-	switch (port_mode)
-	{
+	switch (port_mode) {
+	
 	/* 1 - T1 B8ZS */
 	case CFG_FRAME_SF:
 		pci_write_32((u_int32_t *) &comet->cdrc_cfg, 0);
@@ -288,8 +288,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 
     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
     /* note "rate bits can only be set once after reset" */
-	if (clockmaster)
-		{
+	if (clockmaster) {
+		
 		/* CMODE == clockMode, 0=clock master (so all 3 others should be slave) */
 		/* rate = 1.544 Mb/s */
 		if (isT1mode)
@@ -304,8 +304,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 
 		/* Master Mode i.e.FPMODE=0 (@0x20) */
 		pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
-		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL)
-			{
+		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
+			
 			if (cxt1e1_log_level >= LOG_SBEBUG12)
 				pr_info(">> %s: clockmaster internal clock\n", __func__);
 			/* internal oscillator */
@@ -424,8 +424,8 @@  WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
 {
 	u_int32_t sample, unit;
 
-	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++)
-		{
+	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
+		
 		for (unit = 0; unit < COMET_NUM_UNITS; unit++)
 			WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
 		}
@@ -556,8 +556,8 @@  SetCometOps(comet_t *comet)
 {
 	volatile u_int8_t rd_value;
 
-	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2))
-	{
+	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
+	
 		/* read the BRIF Configuration */
 		rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
 		rd_value &= ~0x20;
diff --git a/drivers/staging/cxt1e1/comet.h b/drivers/staging/cxt1e1/comet.h
index c9ae538..4025bbc 100644
--- a/drivers/staging/cxt1e1/comet.h
+++ b/drivers/staging/cxt1e1/comet.h
@@ -25,8 +25,8 @@ 
 
 #define VINT32  volatile u_int32_t
 
-struct s_comet_reg
-{
+struct s_comet_reg {
+
 VINT32 gbl_cfg;      /* 00  Global Cfg */
 VINT32 clkmon;       /* 01  Clk Monitor */
 VINT32 rx_opt;       /* 02  RX Options */
@@ -122,7 +122,7 @@  VINT32 ibcd_deact;       /* 4F  IBCD Deactivate Code */
 VINT32 sigx_cfg;         /* 50  SIGX Cfg/Change of Signaling State */
 VINT32 sigx_acc_cos;     /* 51  SIGX uP Access Sts/Change of Signaling State */
 VINT32 sigx_iac_cos;     /* 52  SIGX Channel Indirect
-                              * Addr/Ctl/Change of Signaling State */
+	                              * Addr/Ctl/Change of Signaling State */
 VINT32 sigx_idb_cos;     /* 53  SIGX Channel Indirect Data
                               * Buffer/Change of Signaling State */
 
@@ -236,6 +236,7 @@  VINT32 __resAF;          /* AF     Reserved */
 VINT32 tdpr2_cfg;        /* B0  TDPR #2 Cfg */
 VINT32 tdpr2_utl;        /* B1  TDPR #2 Upper TX Threshold */
 VINT32 tdpr2_ltl;        /* B2  TDPR #2 Lower TX Threshold */
+
 VINT32 tdpr2_ien;        /* B3  TDPR #2 Intr Enable */
 VINT32 tdpr2_ists;       /* B4  TDPR #2 Intr Sts/UDR Clear */
 VINT32 tdpr2_data;       /* B5  TDPR #2 TX Data */