[OPW,kernel] Staging:cxt1e1:comet.c: Fix the line length exceeding 80 characters
diff mbox

Message ID 1381221496-3093-1-git-send-email-archanakumari959@gmail.com
State Changes Requested
Headers show

Commit Message

Archana kumari Oct. 8, 2013, 8:38 a.m. UTC
Fixes the following coding style issue :" line over 80 characters "in the file
detected via checkpatch.pl

Signed-off-by: Archana kumari <archanakumari959@gmail.com>
---
 drivers/staging/cxt1e1/comet.c | 58 +++++++++++++++++++++++++++---------------
 1 file changed, 38 insertions(+), 20 deletions(-)

Comments

Greg Kroah-Hartman Oct. 11, 2013, 7:55 p.m. UTC | #1
On Tue, Oct 08, 2013 at 02:08:16PM +0530, Archana kumari wrote:
>  Fixes the following coding style issue :" line over 80 characters "in the file

Which file?

A few comments below on this patch:

> @@ -146,9 +147,10 @@ void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
>  	 /* t1RBOC enable(BOC:BitOriented Code) */
>  	pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
>  	if (isT1mode) {
> -	

This wasn't a "line over 80 characters" warning that you fixed.

>  
> -	/* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
> +
> +	/* IBCD cfg: aka Inband Code Detection ** loopback
> +			code length set to */
>  		/* 6 bit down, 5 bit up (assert) */

Multiple line comments should be in the form:
	/*
	 * IBCD cfg: aka Inband Code Detection ** loopback code length set to
	 * 6 bit down, 5 bit up (assert)
	 */

The file, Documentation/CodingStyle decribes this pretty well, right?

You do this in a few other places in this patch.

>  			if (cxt1e1_log_level >= LOG_SBEBUG12)
> -				pr_info(">> %s: clockmaster external clock\n", __func__);
> +				pr_info(">> %s: clockmaster external
> +						clock\n", __func__);

This is an "odd" change, you just added a bunch of whitespace to the
string, which I don't think is what you intended to do, right?

Care to fix this all up and resend?

thanks,

greg k-h

Patch
diff mbox

diff --git a/drivers/staging/cxt1e1/comet.c b/drivers/staging/cxt1e1/comet.c
index 66160bc..8746789 100644
--- a/drivers/staging/cxt1e1/comet.c
+++ b/drivers/staging/cxt1e1/comet.c
@@ -30,7 +30,8 @@  extern int  cxt1e1_log_level;
 /* forward references */
 static void SetPwrLevel(comet_t *comet);
 static void WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table);
-static void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet, u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
+static void WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
+		u_int8_t table[COMET_NUM_SAMPLES][COMET_NUM_UNITS]);
 
 
 void       *TWV_table[12] = {
@@ -146,9 +147,10 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 	 /* t1RBOC enable(BOC:BitOriented Code) */
 	pci_write_32((u_int32_t *) &comet->t1_rboc_ena, 0x00);
 	if (isT1mode) {
-	
 
-	/* IBCD cfg: aka Inband Code Detection ** loopback code length set to */
+
+	/* IBCD cfg: aka Inband Code Detection ** loopback
+			code length set to */
 		/* 6 bit down, 5 bit up (assert) */
 		pci_write_32((u_int32_t *) &comet->ibcd_cfg, 0x04);
 		/* line loopback activate pattern */
@@ -288,7 +290,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
     /* 0x30: "BRIF cfg"; 0x20 is 'CMODE', 0x03 is (bit) rate */
     /* note "rate bits can only be set once after reset" */
 	if (clockmaster) {
-		/* CMODE == clockMode, 0=clock master (so all 3 others should be				 slave) */
+		/* CMODE == clockMode, 0=clock master
+			(so all 3 others should be slave) */
 		/* rate = 1.544 Mb/s */
 		if (isT1mode)
 			/* Comet 0 Master Mode(CMODE=0) */
@@ -302,15 +305,18 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 
 		/* Master Mode i.e.FPMODE=0 (@0x20) */
 		pci_write_32((u_int32_t *) &comet->brif_fpcfg, 0x00);
-		if ((moreParams & CFG_CLK_PORT_MASK) == CFG_CLK_PORT_INTERNAL) {
+	        if ((moreParams & CFG_CLK_PORT_MASK)
+				 == CFG_CLK_PORT_INTERNAL) {
 			if (cxt1e1_log_level >= LOG_SBEBUG12)
-				pr_info(">> %s: clockmaster internal clock\n", __func__);
+				pr_info(">> %s: clockmaster internal
+						clock\n", __func__);
 			/* internal oscillator */
 			pci_write_32((u_int32_t *) &comet->tx_time, 0x0d);
 		} else {
 			/* external clock source */
 			if (cxt1e1_log_level >= LOG_SBEBUG12)
-				pr_info(">> %s: clockmaster external clock\n", __func__);
+				pr_info(">> %s: clockmaster external
+						clock\n", __func__);
 			/* loop timing(external) */
 			pci_write_32((u_int32_t *) &comet->tx_time, 0x09);
 		}
@@ -398,7 +404,8 @@  void init_comet(void *ci, comet_t *comet, u_int32_t port_mode, int clockmaster,
 ** Returns:     Nothing
 */
 static void
-WrtXmtWaveform(ci_t *ci, comet_t *comet, u_int32_t sample, u_int32_t unit, u_int8_t data)
+WrtXmtWaveform(ci_t *ci, comet_t *comet,
+		u_int32_t sample, u_int32_t unit, u_int8_t data)
 {
 	u_int8_t    WaveformAddr;
 
@@ -423,11 +430,13 @@  WrtXmtWaveformTbl(ci_t *ci, comet_t *comet,
 
 	for (sample = 0; sample < COMET_NUM_SAMPLES; sample++) {
 			for (unit = 0; unit < COMET_NUM_UNITS; unit++)
-			WrtXmtWaveform(ci, comet, sample, unit, table[sample][unit]);
+			WrtXmtWaveform(ci, comet, sample,
+				unit, table[sample][unit]);
 		}
 
     /* Enable transmitter and set output amplitude */
-	pci_write_32((u_int32_t *) &comet->xlpg_cfg, table[COMET_NUM_SAMPLES][0]);
+	pci_write_32((u_int32_t *) &comet->xlpg_cfg,
+			table[COMET_NUM_SAMPLES][0]);
 }
 
 
@@ -455,7 +464,8 @@  WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
 		/* for write order preservation when Optimizing driver */
 		pci_flush_write(ci);
 		/* write the addr, initiate a read */
-		pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
+		pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
+				(u_int8_t) ramaddr);
 		/* for write order preservation when Optimizing driver */
 		pci_flush_write(ci);
 		/*
@@ -468,9 +478,12 @@  WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
 	}
 
 	value = *table++;
-	pci_write_32((u_int32_t *) &comet->rlps_idata3, (u_int8_t) (value >> 24));
-	pci_write_32((u_int32_t *) &comet->rlps_idata2, (u_int8_t) (value >> 16));
-	pci_write_32((u_int32_t *) &comet->rlps_idata1, (u_int8_t) (value >> 8));
+	pci_write_32((u_int32_t *) &comet->rlps_idata3,
+			(u_int8_t) (value >> 24));
+	pci_write_32((u_int32_t *) &comet->rlps_idata2,
+			(u_int8_t) (value >> 16));
+	pci_write_32((u_int32_t *) &comet->rlps_idata1,
+			(u_int8_t) (value >> 8));
 	pci_write_32((u_int32_t *) &comet->rlps_idata0, (u_int8_t) value);
 	 /* for write order preservation when Optimizing driver */
 	pci_flush_write(ci);
@@ -482,7 +495,8 @@  WrtRcvEqualizerTbl(ci_t *ci, comet_t *comet, u_int32_t *table)
 		/* for write order preservation when optimizing driver */
 		pci_flush_write(ci);
 		/* write the addr, initiate a read */
-		pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr, (u_int8_t) ramaddr);
+		pci_write_32((u_int32_t *) &comet->rlps_eq_iaddr,
+				(u_int8_t) ramaddr);
 		 /* for write order preservation when optimizing driver */
 		pci_flush_write(ci);
 
@@ -553,15 +567,19 @@  SetCometOps(comet_t *comet)
 	volatile u_int8_t rd_value;
 
 	if (comet == mConfig.C4Func1Base + (COMET0_OFFSET >> 2)) {
-	
+
 		/* read the BRIF Configuration */
-		rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);
+		rd_value = (u_int8_t) pci_read_32
+				((u_int32_t *) &comet->brif_cfg);
 		rd_value &= ~0x20;
-		pci_write_32((u_int32_t *) &comet->brif_cfg, (u_int32_t) rd_value);
+		pci_write_32((u_int32_t *) &comet->brif_cfg,
+				(u_int32_t) rd_value);
 		/* read the BRIF Frame Pulse Configuration */
-		rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_fpcfg);
+		rd_value = (u_int8_t) pci_read_32
+				((u_int32_t *) &comet->brif_fpcfg);
 		rd_value &= ~0x20;
-		pci_write_32((u_int32_t *) &comet->brif_fpcfg, (u_int8_t) rd_value);
+		pci_write_32((u_int32_t *) &comet->brif_fpcfg,
+				(u_int8_t) rd_value);
 	} else {
 	/* read the BRIF Configuration */
 	rd_value = (u_int8_t) pci_read_32((u_int32_t *) &comet->brif_cfg);