[OPW,kernel,v2] staging:dgnc:Fixes line above 80 characters in dgnc_cls.h
diff mbox

Message ID 1381934058-22754-1-git-send-email-archanakumari959@gmail.com
State Rejected
Headers show

Commit Message

Archana kumari Oct. 16, 2013, 2:34 p.m. UTC
Fixes the warning "line above 80 characters " in staging:dgnc:dgnc_cls.h
detected via checkpatch.pl

Signed-off-by: Archana kumari <archanakumari959@gmail.com>
---
 drivers/staging/dgnc/dgnc_cls.h | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

Comments

Greg Kroah-Hartman Oct. 16, 2013, 3:04 p.m. UTC | #1
On Wed, Oct 16, 2013 at 08:04:18PM +0530, Archana kumari wrote:
> Fixes the warning "line above 80 characters " in staging:dgnc:dgnc_cls.h
> detected via checkpatch.pl
> 
> Signed-off-by: Archana kumari <archanakumari959@gmail.com>
> ---
>  drivers/staging/dgnc/dgnc_cls.h | 15 ++++++++++-----
>  1 file changed, 10 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h
> index ffe8535..9e5f946 100644
> --- a/drivers/staging/dgnc/dgnc_cls.h
> +++ b/drivers/staging/dgnc/dgnc_cls.h
> @@ -38,7 +38,8 @@
>  struct cls_uart_struct {
>  	u8 txrx;		/* WR  RHR/THR - Holding Reg */
>  	u8 ier;		/* WR  IER - Interrupt Enable Reg */
> -	u8 isr_fcr;		/* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
> +	u8 isr_fcr;
> +/* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg */

Again, look at this, do you really think this is the best way to have
the code read now?  Does this change make sense?

Please always understand what you are fixing up, and why you are fixing
it, don't just blindly make checkpatch cleanup fixes without knowing why
you are making them.


>  	u8 lcr;		/* WR  LCR - Line Control Reg */
>  	u8 mcr;		/* WR  MCR - Modem Control Reg */
>  	u8 lsr;		/* WR  LSR - Line Status Reg */
> @@ -61,8 +62,10 @@ struct cls_uart_struct {
>  #define UART_16654_FCR_RXTRIGGER_56	0x80
>  #define UART_16654_FCR_RXTRIGGER_60     0xC0
>  
> -#define UART_IIR_XOFF			0x10	/* Received Xoff signal/Special character */
> -#define UART_IIR_CTSRTS			0x20	/* Received CTS/RTS change of state */
> +#define UART_IIR_XOFF			0x10
> +/* Received Xoff signal/Special character */
> +#define UART_IIR_CTSRTS			0x20
> +/* Received CTS/RTS change of state */

Same here, does this make sense?

greg k-h

Patch
diff mbox

diff --git a/drivers/staging/dgnc/dgnc_cls.h b/drivers/staging/dgnc/dgnc_cls.h
index ffe8535..9e5f946 100644
--- a/drivers/staging/dgnc/dgnc_cls.h
+++ b/drivers/staging/dgnc/dgnc_cls.h
@@ -38,7 +38,8 @@ 
 struct cls_uart_struct {
 	u8 txrx;		/* WR  RHR/THR - Holding Reg */
 	u8 ier;		/* WR  IER - Interrupt Enable Reg */
-	u8 isr_fcr;		/* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
+	u8 isr_fcr;
+/* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
 	u8 lcr;		/* WR  LCR - Line Control Reg */
 	u8 mcr;		/* WR  MCR - Modem Control Reg */
 	u8 lsr;		/* WR  LSR - Line Status Reg */
@@ -61,8 +62,10 @@  struct cls_uart_struct {
 #define UART_16654_FCR_RXTRIGGER_56	0x80
 #define UART_16654_FCR_RXTRIGGER_60     0xC0
 
-#define UART_IIR_XOFF			0x10	/* Received Xoff signal/Special character */
-#define UART_IIR_CTSRTS			0x20	/* Received CTS/RTS change of state */
+#define UART_IIR_XOFF			0x10
+/* Received Xoff signal/Special character */
+#define UART_IIR_CTSRTS			0x20
+/* Received CTS/RTS change of state */
 #define UART_IIR_RDI_TIMEOUT		0x0C    /* Receiver data TIMEOUT */
 
 /*
@@ -75,8 +78,10 @@  struct cls_uart_struct {
 #define UART_EXAR654_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
 #define UART_EXAR654_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
 
-#define UART_EXAR654_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char  */
-#define UART_EXAR654_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
+#define UART_EXAR654_XOFF_DETECT  0x1
+/* Indicates whether chip saw an incoming XOFF char */
+#define UART_EXAR654_XON_DETECT   0x2
+/* Indicates whether chip saw an incoming XON char */
 
 #define UART_EXAR654_IER_XOFF     0x20    /* Xoff Interrupt Enable */
 #define UART_EXAR654_IER_RTSDTR   0x40    /* Output Interrupt Enable */