[v2,1/8] clk: sunxi: add clock-output-names dt property support
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Message ID 1388987892-23733-2-git-send-email-wens@csie.org
State New, archived
Headers show

Commit Message

Chen-Yu Tsai (Moxa) Jan. 6, 2014, 5:58 a.m. UTC
sunxi clock drivers use dt node name as clock name, but clock
nodes should be named clk@X, so the names would be the same.
Let the drivers read clock names from dt clock-output-names
property.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
 1 file changed, 6 insertions(+)

Comments

Maxime Ripard Jan. 7, 2014, 10:14 p.m. UTC | #1
Hi Chen-Yu,

On Mon, Jan 06, 2014 at 01:58:05PM +0800, Chen-Yu Tsai wrote:
> sunxi clock drivers use dt node name as clock name, but clock
> nodes should be named clk@X, so the names would be the same.
> Let the drivers read clock names from dt clock-output-names
> property.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/clk/sunxi/clk-sunxi.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index 19d9e9e..14a3774 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -53,6 +53,8 @@ static void __init sun4i_osc_clk_setup(struct device_node *node)
>  	if (of_property_read_u32(node, "clock-frequency", &rate))
>  		return;
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	/* set up gate and fixed rate properties */
>  	gate->reg = of_iomap(node, 0);
>  	gate->bit_idx = SUNXI_OSC24M_GATE;
> @@ -595,6 +597,8 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
>  	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
>  		i++;
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	clk = clk_register_mux(NULL, clk_name, parents, i,
>  			       CLK_SET_RATE_NO_REPARENT, reg,
>  			       data->shift, SUNXI_MUX_GATE_WIDTH,
> @@ -654,6 +658,8 @@ static void __init sunxi_divider_clk_setup(struct device_node *node,
>  
>  	clk_parent = of_clk_get_parent_name(node, 0);
>  
> +	of_property_read_string(node, "clock-output-names", &clk_name);
> +
>  	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
>  				   reg, data->shift, data->width,
>  				   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
> -- 
> 1.8.5.2
> 

Please document this in Documentation/devicetree/bindings.

Thanks!
Maxime
Chen-Yu Tsai (Moxa) Jan. 8, 2014, 1:44 a.m. UTC | #2
Hi,

On Wed, Jan 8, 2014 at 6:14 AM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi Chen-Yu,
>
> On Mon, Jan 06, 2014 at 01:58:05PM +0800, Chen-Yu Tsai wrote:
>> sunxi clock drivers use dt node name as clock name, but clock
>> nodes should be named clk@X, so the names would be the same.
>> Let the drivers read clock names from dt clock-output-names
>> property.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>
> Please document this in Documentation/devicetree/bindings.
>

Do you want them in the same patch, or separate?

I think someone asked about this yesterday, but don't remember
the conclusion.


Thanks
ChenYu

Patch
diff mbox

diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 19d9e9e..14a3774 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -53,6 +53,8 @@  static void __init sun4i_osc_clk_setup(struct device_node *node)
 	if (of_property_read_u32(node, "clock-frequency", &rate))
 		return;
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	/* set up gate and fixed rate properties */
 	gate->reg = of_iomap(node, 0);
 	gate->bit_idx = SUNXI_OSC24M_GATE;
@@ -595,6 +597,8 @@  static void __init sunxi_mux_clk_setup(struct device_node *node,
 	       (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
 		i++;
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	clk = clk_register_mux(NULL, clk_name, parents, i,
 			       CLK_SET_RATE_NO_REPARENT, reg,
 			       data->shift, SUNXI_MUX_GATE_WIDTH,
@@ -654,6 +658,8 @@  static void __init sunxi_divider_clk_setup(struct device_node *node,
 
 	clk_parent = of_clk_get_parent_name(node, 0);
 
+	of_property_read_string(node, "clock-output-names", &clk_name);
+
 	clk = clk_register_divider(NULL, clk_name, clk_parent, 0,
 				   reg, data->shift, data->width,
 				   data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,