diff mbox

Wierd code in Entry.S

Message ID 20090711010513.38B824FE2@hiauly1.hia.nrc.ca (mailing list archive)
State Superseded
Headers show

Commit Message

John David Anglin July 11, 2009, 1:05 a.m. UTC
> It looks to me like these macros can be deleted.  For example, the PA 1.x
> depi mneumonic is equivalent to the PA 2.0 depwi mneumonic.  See Table
> J-2 in PA 2.0 arch.  There's no need for the 64-bit versions.  The PA 1.x
> mneumonics are still valid in PA 2.0 assembler.  However, I would suggest
> that the PA 2.0 mneumonics be used in PA 2.0 specific code.

The following still boots (64-bit UP kernel).

Dave

Comments

kyle mcmartin July 13, 2009, 1:15 a.m. UTC | #1
On Sun, Jul 12, 2009 at 03:40:34PM -0400, John David Anglin wrote:
> > > It looks to me like these macros can be deleted.  For example, the PA 1.x
> > > depi mneumonic is equivalent to the PA 2.0 depwi mneumonic.  See Table
> > > J-2 in PA 2.0 arch.  There's no need for the 64-bit versions.  The PA 1.x
> > > mneumonics are still valid in PA 2.0 assembler.  However, I would suggest
> > > that the PA 2.0 mneumonics be used in PA 2.0 specific code.
> 
> Sorry, the macros can't be removed.  The PA 1.x mneumonics result in undefined
> behavior in the most sign-significant 32 bits.  The should just be renamed.
> 

Can someone distill all these mails into a patch? It will directly apply
to upstream and all the current stable releases, so a single patch
should suffice.

I'd do it myself, but I'm too busy writing a paper this week. :/

regards, Kyle
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diff mbox

Patch

diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index ae3e70c..896791a 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -364,32 +364,6 @@ 
 	.align		32
 	.endm
 
-	/* The following are simple 32 vs 64 bit instruction
-	 * abstractions for the macros */
-	.macro		EXTR	reg1,start,length,reg2
-#ifdef CONFIG_64BIT
-	extrd,u		\reg1,32+(\start),\length,\reg2
-#else
-	extrw,u		\reg1,\start,\length,\reg2
-#endif
-	.endm
-
-	.macro		DEP	reg1,start,length,reg2
-#ifdef CONFIG_64BIT
-	depd		\reg1,32+(\start),\length,\reg2
-#else
-	depw		\reg1,\start,\length,\reg2
-#endif
-	.endm
-
-	.macro		DEPI	val,start,length,reg
-#ifdef CONFIG_64BIT
-	depdi		\val,32+(\start),\length,\reg
-#else
-	depwi		\val,\start,\length,\reg
-#endif
-	.endm
-
 	/* In LP64, the space contains part of the upper 32 bits of the
 	 * fault.  We have to extract this and place it in the va,
 	 * zeroing the corresponding bits in the space register */
@@ -442,19 +416,19 @@ 
 	 */
 	.macro		L2_ptep	pmd,pte,index,va,fault
 #if PT_NLEVELS == 3
-	EXTR		\va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
+	extru		\va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
 #else
-	EXTR		\va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
+	extru		\va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
 #endif
-	DEP             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
+	dep             %r0,31,PAGE_SHIFT,\pmd  /* clear offset */
 	copy		%r0,\pte
 	ldw,s		\index(\pmd),\pmd
 	bb,>=,n		\pmd,_PxD_PRESENT_BIT,\fault
-	DEP		%r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
+	dep		%r0,31,PxD_FLAG_SHIFT,\pmd /* clear flags */
 	copy		\pmd,%r9
 	SHLREG		%r9,PxD_VALUE_SHIFT,\pmd
-	EXTR		\va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
-	DEP		%r0,31,PAGE_SHIFT,\pmd  /* clear offset */
+	extru		\va,31-PAGE_SHIFT,ASM_BITS_PER_PTE,\index
+	dep		%r0,31,PAGE_SHIFT,\pmd  /* clear offset */
 	shladd		\index,BITS_PER_PTE_ENTRY,\pmd,\pmd
 	LDREG		%r0(\pmd),\pte		/* pmd is now pte */
 	bb,>=,n		\pte,_PAGE_PRESENT_BIT,\fault
@@ -553,7 +527,7 @@ 
 	 * on most of those machines only handles cache transactions.
 	 */
 	extrd,u,*=	\pte,_PAGE_NO_CACHE_BIT+32,1,%r0
-	depi		1,12,1,\prot
+	depdi		1,12,1,\prot
 
 	/* Drop prot bits and convert to page addr for iitlbt and idtlbt */
 	convert_for_tlb_insert20 \pte
@@ -605,7 +579,7 @@ 
 	depdi		0,31,32,\tmp
 #endif
 	copy		\va,\tmp1
-	DEPI		0,31,23,\tmp1
+	depi		0,31,23,\tmp1
 	cmpb,COND(<>),n	\tmp,\tmp1,\fault
 	ldi		(_PAGE_DIRTY|_PAGE_WRITE|_PAGE_READ),\prot
 	depd,z		\prot,8,7,\prot