drm/i915: fix 845G FIFO size & burst length
diff mbox

Message ID 20090722125459.22d6df83@jbarnes-g45
State Accepted
Headers show

Commit Message

Jesse Barnes July 22, 2009, 7:54 p.m. UTC
I had one report of flicker due to FIFO underruns on 845G.  Scott was
kind enough to test a few patches and report success with this one.
Looks like 845G measures FIFO size slightly differently than other
chips, and we were also clobbering the FIFO burst length.  Fixing both
of those issues gives him a healthy machine again.

Note that we still only adjust plane A's watermark in the 830/845
case.  If someone is willing to test we could support a bigger variety
of dual-head 830/845 configurations with a bit more code.

Fixes fdo bug #19304 (again).

Reported-by: Scott Hansen <scottandchrystie@comcast.net>
Tested-by: Scott Hansen <scottandchrystie@comcast.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Comments

Dave Airlie July 22, 2009, 8:26 p.m. UTC | #1
On Thu, Jul 23, 2009 at 5:54 AM, Jesse Barnes<jbarnes@virtuousgeek.org> wrote:
> I had one report of flicker due to FIFO underruns on 845G.  Scott was
> kind enough to test a few patches and report success with this one.
> Looks like 845G measures FIFO size slightly differently than other
> chips, and we were also clobbering the FIFO burst length.  Fixing both
> of those issues gives him a healthy machine again.
>
> Note that we still only adjust plane A's watermark in the 830/845
> case.  If someone is willing to test we could support a bigger variety
> of dual-head 830/845 configurations with a bit more code.

I don't think 845 ever had a second pipe/plane in it.

from memory 845G and 865G were single crtc chips for desktops.

Dave.
Jesse Barnes July 22, 2009, 8:50 p.m. UTC | #2
On Thu, 23 Jul 2009 06:26:57 +1000
Dave Airlie <airlied@gmail.com> wrote:

> On Thu, Jul 23, 2009 at 5:54 AM, Jesse
> Barnes<jbarnes@virtuousgeek.org> wrote:
> > I had one report of flicker due to FIFO underruns on 845G.  Scott
> > was kind enough to test a few patches and report success with this
> > one. Looks like 845G measures FIFO size slightly differently than
> > other chips, and we were also clobbering the FIFO burst length.
> >  Fixing both of those issues gives him a healthy machine again.
> >
> > Note that we still only adjust plane A's watermark in the 830/845
> > case.  If someone is willing to test we could support a bigger
> > variety of dual-head 830/845 configurations with a bit more code.
> 
> I don't think 845 ever had a second pipe/plane in it.
> 
> from memory 845G and 865G were single crtc chips for desktops.

Yeah, should have just said 830M.

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a58bfad..1f15652 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1844,6 +1844,9 @@  static int intel_get_fifo_size(struct drm_device *dev, int plane)
 			size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
 				(dsparb & 0x1ff);
 		size >>= 1; /* Convert to cachelines */
+	} else if (IS_845G(dev)) {
+		size = dsparb & 0x7f;
+		size >>= 2; /* Convert to cachelines */
 	} else {
 		size = dsparb & 0x7f;
 		size >>= 1; /* Convert to cachelines */
@@ -1943,14 +1946,16 @@  static void i830_update_wm(struct drm_device *dev, int planea_clock,
 			   int pixel_size)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK;
+	uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
 	int planea_wm;
 
 	i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0);
 
 	planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
 				       pixel_size, latency_ns);
-	fwater_lo = fwater_lo | planea_wm;
+	fwater_lo |= (3<<8) | planea_wm;
+
+	DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm);
 
 	I915_WRITE(FW_BLC, fwater_lo);
 }