From patchwork Wed Jul 22 19:54:59 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 36890 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n6MJt4Gn030558 for ; Wed, 22 Jul 2009 19:55:04 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 81B6D9ED2F; Wed, 22 Jul 2009 12:55:04 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from outbound-mail-158.bluehost.com (outbound-mail-158.bluehost.com [67.222.39.38]) by gabe.freedesktop.org (Postfix) with SMTP id 58D7B9E75A for ; Wed, 22 Jul 2009 12:55:00 -0700 (PDT) Received: (qmail 18021 invoked by uid 0); 22 Jul 2009 19:55:00 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by outboundproxy5.bluehost.com with SMTP; 22 Jul 2009 19:55:00 -0000 Received: from [75.111.28.251] (helo=jbarnes-g45) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.69) (envelope-from ) id 1MThu0-0000Xk-Jo; Wed, 22 Jul 2009 13:55:00 -0600 Date: Wed, 22 Jul 2009 12:54:59 -0700 From: Jesse Barnes To: intel-gfx@lists.freedesktop.org, eric@anholt.net Message-ID: <20090722125459.22d6df83@jbarnes-g45> X-Mailer: Claws Mail 3.6.1 (GTK+ 2.16.1; i486-pc-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 75.111.28.251 authed with jbarnes@virtuousgeek.org} Subject: [Intel-gfx] [PATCH] drm/i915: fix 845G FIFO size & burst length X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.9 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org I had one report of flicker due to FIFO underruns on 845G. Scott was kind enough to test a few patches and report success with this one. Looks like 845G measures FIFO size slightly differently than other chips, and we were also clobbering the FIFO burst length. Fixing both of those issues gives him a healthy machine again. Note that we still only adjust plane A's watermark in the 830/845 case. If someone is willing to test we could support a bigger variety of dual-head 830/845 configurations with a bit more code. Fixes fdo bug #19304 (again). Reported-by: Scott Hansen Tested-by: Scott Hansen Signed-off-by: Jesse Barnes diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index a58bfad..1f15652 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1844,6 +1844,9 @@ static int intel_get_fifo_size(struct drm_device *dev, int plane) size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - (dsparb & 0x1ff); size >>= 1; /* Convert to cachelines */ + } else if (IS_845G(dev)) { + size = dsparb & 0x7f; + size >>= 2; /* Convert to cachelines */ } else { size = dsparb & 0x7f; size >>= 1; /* Convert to cachelines */ @@ -1943,14 +1946,16 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int pixel_size) { struct drm_i915_private *dev_priv = dev->dev_private; - uint32_t fwater_lo = I915_READ(FW_BLC) & MM_FIFO_WATERMARK; + uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff; int planea_wm; i830_wm_info.fifo_size = intel_get_fifo_size(dev, 0); planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info, pixel_size, latency_ns); - fwater_lo = fwater_lo | planea_wm; + fwater_lo |= (3<<8) | planea_wm; + + DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm); I915_WRITE(FW_BLC, fwater_lo); }