diff mbox

i915: Modify for pineview clock source and lvds sync polarity

Message ID AANLkTimLCt9Jbg7x=hYDYsisc6TvOwjHd9vybswR=7aC@mail.gmail.com (mailing list archive)
State New, archived
Headers show

Commit Message

Bryan Freed Dec. 8, 2010, 9:46 p.m. UTC
None
diff mbox

Patch

Index: drivers/gpu/drm/i915/i915_reg.h
diff --git a/drivers/gpu/drm/i915/i915_reg.h
b/drivers/gpu/drm/i915/i915_reg.h
index
b463a0baa924ff1dee74ca8473b458927cfa0901..e325eaea4bfb289c76a093c5cada026eab6c3983
100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1056,6 +1056,10 @@ 
 #define   LVDS_PIPEB_SELECT (1 << 30)
 /* LVDS dithering flag on 965/g4x platform */
 #define   LVDS_ENABLE_DITHER (1 << 25)
+/* LVDS sync polarity flags. Set to invert (i.e. negative) */
+#define   LVDS_VSYNC_POLARITY (1 << 21)
+#define   LVDS_HSYNC_POLARITY (1 << 20)
+
 /* Enable border for unscaled (or aspect-scaled) display */
 #define   LVDS_BORDER_ENABLE (1 << 15)
 /*
Index: drivers/gpu/drm/i915/intel_bios.c
diff --git a/drivers/gpu/drm/i915/intel_bios.c
b/drivers/gpu/drm/i915/intel_bios.c
index
943bbad066af79d6fc62891014f15479213aa34e..e2f3629b46a028077aee214bbc323a1b3ca9ca8f
100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -506,6 +506,14 @@  init_vbt_defaults(struct drm_i915_private *dev_priv)
  dev_priv->int_tv_support = 1;
  dev_priv->int_crt_support = 1;

+ if (IS_PINEVIEW(dev_priv->dev)) {
+ /* On Pineview flip default to use SSC (VBT can override) */
+ dev_priv->lvds_use_ssc = 1;
+ /* The ssc pin gets 100MHz downspread from timing gen */
+ dev_priv->lvds_ssc_freq = 100;
+ } else {
+ dev_priv->lvds_use_ssc = 0;
+ }
  /* Set the Panel Power On/Off timings if uninitialized. */
  if ((I915_READ(PP_ON_DELAYS) == 0) && (I915_READ(PP_OFF_DELAYS) == 0)) {
  /* Set T2 to 40ms and T5 to 200ms */
Index: drivers/gpu/drm/i915/intel_display.c
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index
787e6da01984a2c2296295359250cd436e0cf5fe..48d5994ade661d3213a712512f3e6c96c87dbd1f
100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3334,6 +3334,18 @@  static int intel_crtc_mode_set(struct drm_crtc *crtc,
  lvds &= ~LVDS_ENABLE_DITHER;
  }
  }
+ /* Only tested on pineview, should work on IS_9XX */
+ if (IS_PINEVIEW(dev)) {
+ /* Set sync polarity for case when vbios did not */
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ lvds |= LVDS_HSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
+ lvds &= ~LVDS_HSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ lvds |= LVDS_VSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
+ lvds &= ~LVDS_VSYNC_POLARITY;
+ }
  I915_WRITE(lvds_reg, lvds);
  I915_READ(lvds_reg);
  }