[v6,3/5] devicetree: bindings: Document Krait cache error interrupts
diff mbox

Message ID 1396641450-12854-4-git-send-email-sboyd@codeaurora.org
State New, archived
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Commit Message

Stephen Boyd April 4, 2014, 7:57 p.m. UTC
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
 1 file changed, 47 insertions(+), 1 deletion(-)

Comments

Borislav Petkov April 8, 2014, 3:39 p.m. UTC | #1
On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> The Krait L1/L2 error reporting hardware is made up a per-CPU
> interrupt for the L1 cache and a SPI interrupt for the L2.
> 
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Kumar Gala <galak@codeaurora.org>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
>  1 file changed, 47 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
> index b90fcc7c53cf..d7357e777399 100644
> --- a/Documentation/devicetree/bindings/arm/cache.txt
> +++ b/Documentation/devicetree/bindings/arm/cache.txt

Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html

So whoever picks those patches up, Lorenzo's doc needs to be in his tree
first too.

How about I review the EDAC part and an arm maintainer picks the whole
series up? Would that be easier, logistically?
Stephen Boyd April 8, 2014, 7:55 p.m. UTC | #2
On 04/08/14 08:39, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
>> The Krait L1/L2 error reporting hardware is made up a per-CPU
>> interrupt for the L1 cache and a SPI interrupt for the L2.
>>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Kumar Gala <galak@codeaurora.org>
>> Cc: <devicetree@vger.kernel.org>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>>  Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
>>  1 file changed, 47 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
>> index b90fcc7c53cf..d7357e777399 100644
>> --- a/Documentation/devicetree/bindings/arm/cache.txt
>> +++ b/Documentation/devicetree/bindings/arm/cache.txt
> Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
>
> So whoever picks those patches up, Lorenzo's doc needs to be in his tree
> first too.
>
> How about I review the EDAC part and an arm maintainer picks the whole
> series up? Would that be easier, logistically?
>

That sounds fine if you want to give an ack on the edac changes. I can
route it through arm-soc.
Lorenzo Pieralisi April 29, 2014, 10:34 a.m. UTC | #3
On Tue, Apr 08, 2014 at 04:39:25PM +0100, Borislav Petkov wrote:
> On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
> > The Krait L1/L2 error reporting hardware is made up a per-CPU
> > interrupt for the L1 cache and a SPI interrupt for the L2.
> > 
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Kumar Gala <galak@codeaurora.org>
> > Cc: <devicetree@vger.kernel.org>
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> > ---
> >  Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
> >  1 file changed, 47 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
> > index b90fcc7c53cf..d7357e777399 100644
> > --- a/Documentation/devicetree/bindings/arm/cache.txt
> > +++ b/Documentation/devicetree/bindings/arm/cache.txt
> 
> Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
> 
> So whoever picks those patches up, Lorenzo's doc needs to be in his tree
> first too.

Sorry for the delay in replying. Those cache bindings need an ACK to get
merged, and were introduced so that idle states can retrieve power domain
information for caches. I am going to revive the idle bindings thread
to see what we can/should merge of these bindings as things stand, I
really hope this won't block the series any further, otherwise we can
rework the patches so that this series can get in first, or simplify my
series to allow both to get merged as soon as possible without compromising
future requirements.

Thanks,
Lorenzo

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Borislav Petkov April 29, 2014, 7:02 p.m. UTC | #4
On Tue, Apr 29, 2014 at 11:34:00AM +0100, Lorenzo Pieralisi wrote:
> Sorry for the delay in replying. Those cache bindings need an ACK
> to get merged, and were introduced so that idle states can retrieve
> power domain information for caches. I am going to revive the idle
> bindings thread to see what we can/should merge of these bindings as
> things stand, I really hope this won't block the series any further,
> otherwise we can rework the patches so that this series can get in
> first, or simplify my series to allow both to get merged as soon as
> possible without compromising future requirements.

Right, I think this is Stephen's call. AFAIR, the current state of
affairs is for a followup patchset to come up which I can ack for the
EDAC bits and then another maintainer picks the whole thing up.

Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
index b90fcc7c53cf..d7357e777399 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -37,7 +37,9 @@  This document provides the device tree bindings for ARM architected caches.
 	- compatible
 		Usage: Required
 		Value type: <string>
-		Definition: value shall be "arm,arch-cache".
+		Definition: shall be one of:
+				"arm,arch-cache"
+				"qcom,arch-cache"
 
 	- power-domain
 		Usage: Optional
@@ -45,6 +47,12 @@  This document provides the device tree bindings for ARM architected caches.
 		Definition: A phandle and power domain specifier as defined by
 			    bindings of power domain specified by [3].
 
+	- interrupts
+		Usage: Optional for caches with compatible of "qcom,arch-cache"
+		Value type: <prop-encoded-array>
+		Definition: Error interrupt associated with this cache.
+
+
 Example(dual-cluster big.LITTLE system 32-bit)
 
 	cpus {
@@ -156,6 +164,44 @@  Example(dual-cluster big.LITTLE system 32-bit)
 		};
 	};
 
+Example (Krait 32-bit system):
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "qcom,krait";
+			device_type = "cpu";
+			reg = <0>;
+			next-level-cache = <&L1_0>;
+
+			L1_0: l1-cache {
+				compatible = "qcom,arch-cache";
+				interrupts = <1 14 0x104>;
+				next-level-cache = <&L2>;
+			};
+
+			L2: l2-cache {
+				compatible = "qcom,arch-cache";
+				interrupts = <0 2 0x4>;
+			};
+		};
+
+		cpu@1 {
+			compatible = "qcom,krait";
+			device_type = "cpu";
+			reg = <1>;
+			next-level-cache = <&L1_1>;
+
+			L1_1: l1-cache {
+				compatible = "qcom,arch-cache";
+				interrupts = <1 14 0x204>;
+				next-level-cache = <&L2>;
+			};
+		};
+	};
+
 [1] ARM Architecture Reference Manuals
     http://infocenter.arm.com/help/index.jsp