From patchwork Fri Apr 4 19:57:28 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Boyd X-Patchwork-Id: 3940651 Return-Path: X-Original-To: patchwork-linux-arm-msm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 2C4F79F1EE for ; Fri, 4 Apr 2014 19:59:08 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5DBDA203B6 for ; Fri, 4 Apr 2014 19:59:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 74E2B20395 for ; Fri, 4 Apr 2014 19:59:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753260AbaDDT5j (ORCPT ); Fri, 4 Apr 2014 15:57:39 -0400 Received: from smtp.codeaurora.org ([198.145.11.231]:37901 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753414AbaDDT5f (ORCPT ); Fri, 4 Apr 2014 15:57:35 -0400 Received: from smtp.codeaurora.org (localhost [127.0.0.1]) by smtp.codeaurora.org (Postfix) with ESMTP id CA21B13F12A; Fri, 4 Apr 2014 19:57:34 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 486) id BC5AF13F362; Fri, 4 Apr 2014 19:57:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from sboyd-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: sboyd@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 187A613F12A; Fri, 4 Apr 2014 19:57:34 +0000 (UTC) From: Stephen Boyd To: Borislav Petkov Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, Lorenzo Pieralisi , Mark Rutland , Kumar Gala , Subject: [PATCH v6 3/5] devicetree: bindings: Document Krait cache error interrupts Date: Fri, 4 Apr 2014 12:57:28 -0700 Message-Id: <1396641450-12854-4-git-send-email-sboyd@codeaurora.org> X-Mailer: git-send-email 1.9.0.1.gd5ccf8c In-Reply-To: <1396641450-12854-1-git-send-email-sboyd@codeaurora.org> References: <1396641450-12854-1-git-send-email-sboyd@codeaurora.org> X-Virus-Scanned: ClamAV using ClamSMTP Sender: linux-arm-msm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Krait L1/L2 error reporting hardware is made up a per-CPU interrupt for the L1 cache and a SPI interrupt for the L2. Cc: Lorenzo Pieralisi Cc: Mark Rutland Cc: Kumar Gala Cc: Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt index b90fcc7c53cf..d7357e777399 100644 --- a/Documentation/devicetree/bindings/arm/cache.txt +++ b/Documentation/devicetree/bindings/arm/cache.txt @@ -37,7 +37,9 @@ This document provides the device tree bindings for ARM architected caches. - compatible Usage: Required Value type: - Definition: value shall be "arm,arch-cache". + Definition: shall be one of: + "arm,arch-cache" + "qcom,arch-cache" - power-domain Usage: Optional @@ -45,6 +47,12 @@ This document provides the device tree bindings for ARM architected caches. Definition: A phandle and power domain specifier as defined by bindings of power domain specified by [3]. + - interrupts + Usage: Optional for caches with compatible of "qcom,arch-cache" + Value type: + Definition: Error interrupt associated with this cache. + + Example(dual-cluster big.LITTLE system 32-bit) cpus { @@ -156,6 +164,44 @@ Example(dual-cluster big.LITTLE system 32-bit) }; }; +Example (Krait 32-bit system): + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,krait"; + device_type = "cpu"; + reg = <0>; + next-level-cache = <&L1_0>; + + L1_0: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x104>; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "qcom,arch-cache"; + interrupts = <0 2 0x4>; + }; + }; + + cpu@1 { + compatible = "qcom,krait"; + device_type = "cpu"; + reg = <1>; + next-level-cache = <&L1_1>; + + L1_1: l1-cache { + compatible = "qcom,arch-cache"; + interrupts = <1 14 0x204>; + next-level-cache = <&L2>; + }; + }; + }; + [1] ARM Architecture Reference Manuals http://infocenter.arm.com/help/index.jsp