[v4,2/7] arm64: Decouple page size from level of translation tables
diff mbox

Message ID 000201cf6367$c8084440$5818ccc0$@samsung.com
State New, archived
Headers show

Commit Message

??? April 29, 2014, 4:59 a.m. UTC
This patch separates page size from level of translation tables in
configuration. It facilitates introduction of different options,
such as 4KB + 4 levels, 16KB + 4 levels and 64KB + 3 levels, easily.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Jungseok Lee <jays.lee@samsung.com>
Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com>
---
 arch/arm64/Kconfig                     |   36 +++++++++++++++++++++++++++++++-
 arch/arm64/include/asm/page.h          |    2 +-
 arch/arm64/include/asm/pgalloc.h       |    4 ++--
 arch/arm64/include/asm/pgtable-hwdef.h |    2 +-
 arch/arm64/include/asm/pgtable.h       |    8 +++----
 arch/arm64/include/asm/tlb.h           |    2 +-
 6 files changed, 44 insertions(+), 10 deletions(-)

Comments

Catalin Marinas April 29, 2014, 2:40 p.m. UTC | #1
Jungseok,

On Tue, Apr 29, 2014 at 05:59:20AM +0100, Jungseok Lee wrote:
> +choice
> +	prompt "Level of translation tables"
> +	default ARM64_3_LEVELS if ARM64_4K_PAGES
> +	default ARM64_2_LEVELS if ARM64_64K_PAGES
> +	help
> +	  Allows level of translation tables.
> +
> +config ARM64_2_LEVELS
> +	bool "2 level"
> +	depends on ARM64_64K_PAGES
> +	help
> +	  This feature enables 2 levels of translation tables.
> +
> +config ARM64_3_LEVELS
> +	bool "3 level"
> +	depends on ARM64_4K_PAGES
> +	help
> +	  This feature enables 3 levels of translation tables.
> +
> +endchoice

As I mentioned previously
(http://www.spinics.net/linux/lists/arm-kernel/msg319552.html), just
expose options for the VA space bits rather than the number of levels.
You can still keep the number of levels config options but not visible
in menuconfig (though I think you could also hide them in some header
and avoid config altogether). The VA bits config options can be:

VA_BITS_39 if 4K (3 levels)
VA_BITS_42 if 64K (2 levels)
VA_BITS_47 if 16K (3 levels)
VA_BITS_48 if 4K || 16K || 64K (4/4/3 levels depending on page size)

That's more meaningful to people configuring the kernel.
??? April 30, 2014, 2:44 a.m. UTC | #2
On Tuesday, April 29, 2014 11:41 PM, Catalin Marinas wrote:
> Jungseok,

Hi, Catalin

> On Tue, Apr 29, 2014 at 05:59:20AM +0100, Jungseok Lee wrote:
> > +choice
> > +	prompt "Level of translation tables"
> > +	default ARM64_3_LEVELS if ARM64_4K_PAGES
> > +	default ARM64_2_LEVELS if ARM64_64K_PAGES
> > +	help
> > +	  Allows level of translation tables.
> > +
> > +config ARM64_2_LEVELS
> > +	bool "2 level"
> > +	depends on ARM64_64K_PAGES
> > +	help
> > +	  This feature enables 2 levels of translation tables.
> > +
> > +config ARM64_3_LEVELS
> > +	bool "3 level"
> > +	depends on ARM64_4K_PAGES
> > +	help
> > +	  This feature enables 3 levels of translation tables.
> > +
> > +endchoice
> 
> As I mentioned previously
> (http://www.spinics.net/linux/lists/arm-kernel/msg319552.html), just expose options for the VA space
> bits rather than the number of levels.
> You can still keep the number of levels config options but not visible in menuconfig (though I think
> you could also hide them in some header and avoid config altogether). The VA bits config options can
> be:
> 
> VA_BITS_39 if 4K (3 levels)
> VA_BITS_42 if 64K (2 levels)
> VA_BITS_47 if 16K (3 levels)
> VA_BITS_48 if 4K || 16K || 64K (4/4/3 levels depending on page size)
> 
> That's more meaningful to people configuring the kernel.

Okay, I will revise VA_BITS config as hiding the number of levels.

Best Regards
Jungseok Lee

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Patch
diff mbox

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index e759af5..c7f5d65 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -144,14 +144,48 @@  endmenu
 
 menu "Kernel Features"
 
+choice
+	prompt "Page size"
+	default ARM64_4K_PAGES
+	help
+	  Allows page size.
+
+config ARM64_4K_PAGES
+	bool "4KB"
+	help
+	  This feature enables 4KB pages support.
+
 config ARM64_64K_PAGES
-	bool "Enable 64KB pages support"
+	bool "64KB"
 	help
 	  This feature enables 64KB pages support (4KB by default)
 	  allowing only two levels of page tables and faster TLB
 	  look-up. AArch32 emulation is not available when this feature
 	  is enabled.
 
+endchoice
+
+choice
+	prompt "Level of translation tables"
+	default ARM64_3_LEVELS if ARM64_4K_PAGES
+	default ARM64_2_LEVELS if ARM64_64K_PAGES
+	help
+	  Allows level of translation tables.
+
+config ARM64_2_LEVELS
+	bool "2 level"
+	depends on ARM64_64K_PAGES
+	help
+	  This feature enables 2 levels of translation tables.
+
+config ARM64_3_LEVELS
+	bool "3 level"
+	depends on ARM64_4K_PAGES
+	help
+	  This feature enables 3 levels of translation tables.
+
+endchoice
+
 config CPU_BIG_ENDIAN
        bool "Build big-endian kernel"
        help
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index 46bf666..268e53d 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -33,7 +33,7 @@ 
 
 #ifndef __ASSEMBLY__
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include <asm/pgtable-2level-types.h>
 #else
 #include <asm/pgtable-3level-types.h>
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index 9bea6e7..4829837 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -26,7 +26,7 @@ 
 
 #define check_pgt_cache()		do { } while (0)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
@@ -44,7 +44,7 @@  static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 	set_pud(pud, __pud(__pa(pmd) | PMD_TYPE_TABLE));
 }
 
-#endif	/* CONFIG_ARM64_64K_PAGES */
+#endif	/* CONFIG_ARM64_2_LEVELS */
 
 extern pgd_t *pgd_alloc(struct mm_struct *mm);
 extern void pgd_free(struct mm_struct *mm, pgd_t *pgd);
diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
index 5fc8a66..9cd86c6 100644
--- a/arch/arm64/include/asm/pgtable-hwdef.h
+++ b/arch/arm64/include/asm/pgtable-hwdef.h
@@ -16,7 +16,7 @@ 
 #ifndef __ASM_PGTABLE_HWDEF_H
 #define __ASM_PGTABLE_HWDEF_H
 
-#ifdef CONFIG_ARM64_64K_PAGES
+#ifdef CONFIG_ARM64_2_LEVELS
 #include <asm/pgtable-2level-hwdef.h>
 #else
 #include <asm/pgtable-3level-hwdef.h>
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 90c811f..a64ce5e 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -47,7 +47,7 @@  extern void __pmd_error(const char *file, int line, unsigned long val);
 extern void __pgd_error(const char *file, int line, unsigned long val);
 
 #define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte_val(pte))
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 #define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd_val(pmd))
 #endif
 #define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd_val(pgd))
@@ -320,7 +320,7 @@  static inline pte_t *pmd_page_vaddr(pmd_t pmd)
  */
 #define mk_pte(page,prot)	pfn_pte(page_to_pfn(page),prot)
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 
 #define pud_none(pud)		(!pud_val(pud))
 #define pud_bad(pud)		(!(pud_val(pud) & 2))
@@ -342,7 +342,7 @@  static inline pmd_t *pud_page_vaddr(pud_t pud)
 	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
 }
 
-#endif	/* CONFIG_ARM64_64K_PAGES */
+#endif	/* CONFIG_ARM64_2_LEVELS */
 
 /* to find an entry in a page-table-directory */
 #define pgd_index(addr)		(((addr) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
@@ -353,7 +353,7 @@  static inline pmd_t *pud_page_vaddr(pud_t pud)
 #define pgd_offset_k(addr)	pgd_offset(&init_mm, addr)
 
 /* Find an entry in the second-level page table.. */
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 #define pmd_index(addr)		(((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
 {
diff --git a/arch/arm64/include/asm/tlb.h b/arch/arm64/include/asm/tlb.h
index 80e2c08..bc19101 100644
--- a/arch/arm64/include/asm/tlb.h
+++ b/arch/arm64/include/asm/tlb.h
@@ -91,7 +91,7 @@  static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
 	tlb_remove_page(tlb, pte);
 }
 
-#ifndef CONFIG_ARM64_64K_PAGES
+#ifndef CONFIG_ARM64_2_LEVELS
 static inline void __pmd_free_tlb(struct mmu_gather *tlb, pmd_t *pmdp,
 				  unsigned long addr)
 {