[v2,5/6] ARM: OMAP4: PM: Adds CM1/2 register defs for OMAP4

Message ID	1250087254-28653-5-git-send-email-rnayak@ti.com (mailing list archive)
State	Changes Requested
Delegated to:	Kevin Hilman
Headers	show Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by demeter.kernel.org (8.14.2/8.14.2) with ESMTP id n7CES3jk027333 for <patchwork-omap@patchwork.kernel.org>; Wed, 12 Aug 2009 14:28:06 GMT From: Rajendra Nayak <rnayak@ti.com> To: linux-arm-kernel@lists.arm.linux.org.uk Cc: linux-omap@vger.kernel.org, Rajendra Nayak <rnayak@ti.com> Subject: [PATCH v2 5/6] ARM: OMAP4: PM: Adds CM1/2 register defs for OMAP4 Date: Wed, 12 Aug 2009 19:57:33 +0530 Message-Id: <1250087254-28653-5-git-send-email-rnayak@ti.com> In-Reply-To: <1250087254-28653-4-git-send-email-rnayak@ti.com> References: <1250087254-28653-1-git-send-email-rnayak@ti.com> <1250087254-28653-2-git-send-email-rnayak@ti.com> <1250087254-28653-3-git-send-email-rnayak@ti.com> <1250087254-28653-4-git-send-email-rnayak@ti.com> Sender: linux-omap-owner@vger.kernel.org Precedence: bulk

diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index 1d3c93b..19f7aeb 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -4,10 +4,11 @@ /* * OMAP2/3 Clock Management (CM) register definitions * - * Copyright (C) 2007-2008 Texas Instruments, Inc. + * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2007-2008 Nokia Corporation * * Written by Paul Walmsley + * Updated for OMAP4 by Rajendra Nayak (rnayak@ti.com) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -22,6 +23,10 @@ IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) #define OMAP34XX_CM_REGADDR(module, reg) \ IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) +#define OMAP44XX_CM1_REGADDR(module, reg) \ + IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg)) +#define OMAP44XX_CM2_REGADDR(module, reg) \ + IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg)) /* * Architecture-specific global CM registers @@ -89,6 +94,248 @@ #define OMAP3430_CM_CLKSEL2_EMU 0x0050 #define OMAP3430_CM_CLKSEL3_EMU 0x0054 +#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x0) +#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x8) +#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x10) +#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x20) +#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x24) +#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x28) +#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x2C) +#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x30) +#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x34) +#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x38) +#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x3C) +#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x40) +#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x44) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x48) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x4C) +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x50) +#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x60) +#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x64) +#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x68) +#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x6C) +#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x70) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x88) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x8C) +#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x9C) +#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xA0) +#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xA4) +#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xA8) +#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xAC) +#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xB8) +#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xBC) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xC8) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xCC) +#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xDC) +#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xE0) +#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xE4) +#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xE8) +#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xEC) +#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xF0) +#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0xF4) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x108) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x10C) +#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x120) +#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x124) +#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x128) +#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x12C) +#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x130) +#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x138) +#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x13C) +#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x140) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x148) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x14C) +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x160) +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x164) +#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_MOD, 0x170) +#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x0) +#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x20) +#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x28) +#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x30) +#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x38) +#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x40) +#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x48) +#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x50) +#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x58) +#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x68) +#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x70) +#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x78) +#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x80) +#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_MOD, 0x88) +#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x0) +#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x4) +#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x8) +#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_MOD, 0x20) +#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_DSP_MOD, 0x0) +#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_DSP_MOD, 0x4) +#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_DSP_MOD, 0x8) +#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_DSP_MOD, 0x20) +#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x0) +#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_MOD, 0x40) + +#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x0) +#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x4) +#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x8) +#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x20) +#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_MOD, 0x28) +#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x0) +#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x4) +#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x8) +#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x28) +#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x30) +#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x58) +#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x60) +#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x68) +#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x78) +#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x80) +#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x88) +#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x90) +#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0x98) +#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0xA8) +#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0xC0) +#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_MOD, 0xC8) +#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x0) +#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x4) +#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x8) +#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x20) +#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_MOD, 0x28) +#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x0) +#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x4) +#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x8) +#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x20) +#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_MOD, 0x28) +#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x0) +#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x8) +#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x20) +#define OMAP4430_CM_L4PER_GPTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x28) +#define OMAP4430_CM_L4PER_GPTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x30) +#define OMAP4430_CM_L4PER_GPTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x38) +#define OMAP4430_CM_L4PER_GPTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x40) +#define OMAP4430_CM_L4PER_GPTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x48) +#define OMAP4430_CM_L4PER_GPTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x50) +#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x58) +#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x60) +#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x68) +#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x70) +#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x78) +#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x80) +#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x88) +#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x90) +#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x98) +#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xA0) +#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xA8) +#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xB0) +#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xB8) +#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xC0) +#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xD0) +#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xD8) +#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xE0) +#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xE8) +#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xF0) +#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0xF8) +#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x100) +#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x108) +#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x120) +#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x128) +#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x130) +#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x140) +#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x148) +#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x150) +#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x158) +#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x160) +#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x180) +#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x184) +#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x188) +#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1A0) +#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1A8) +#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1B0) +#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1B8) +#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1C0) +#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1C8) +#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_MOD, 0x1D8) +#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x0) +#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x4) +#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x8) +#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_MOD, 0x20) +#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x0) +#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x8) +#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x20) +#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x100) +#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x108) +#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x120) +#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x128) +#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x130) +#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x200) +#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x204) +#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x208) +#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x220) +#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x300) +#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x304) +#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x308) +#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x320) +#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x400) +#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x420) +#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x428) +#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x430) +#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x438) +#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x440) +#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x450) +#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x458) +#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x460) +#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x500) +#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x504) +#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x508) +#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x520) +#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x528) +#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x600) +#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x608) +#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x620) +#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x628) +#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x630) +#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x638) +#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x700) +#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x720) +#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x728) +#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_MOD, 0x740) +#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x0) +#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_MOD, 0x20) +#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x0) +#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_MOD, 0x40) +#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x0) +#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x4) +#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x8) +#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x10) +#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x14) +#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x18) +#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x1C) +#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x24) +#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x28) +#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x2C) +#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x30) +#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x38) +#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x40) +#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x44) +#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x48) +#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x4C) +#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x50) +#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x54) +#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x58) +#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x5C) +#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x60) +#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x64) +#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x68) +#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x6C) +#define OMAP4430_CM_EMU_OVERRIDE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x70) +#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x80) +#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x84) +#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x88) +#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x8C) +#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_MOD, 0x90) +#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x0) +#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x20) +#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x28) +#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x30) +#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_MOD, 0x38) /* Clock management domain register get/set */ diff --git a/arch/arm/mach-omap2/cm1-regbits-44xx.h b/arch/arm/mach-omap2/cm1-regbits-44xx.h new file mode 100644 index 0000000..184f6b0 --- /dev/null +++ b/arch/arm/mach-omap2/cm1-regbits-44xx.h @@ -0,0 +1,161 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_CM1_REGBITS_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CM1_REGBITS_44XX_H + +/* + * OMAP4430 Clock Management Module1 register bits + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Written by Rajendra Nayak (rnayak@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "cm.h" + +#define OMAP4430_CLKSEL_L4 (1 << 8) +#define OMAP4430_CM_CLKSEL_CORE_CLKSEL_L3 (1 << 4) +#define OMAP4430_CLKSEL_CORE (1 << 0) +#define OMAP4430_PAD_CLKS_GATE (1 << 8) +#define OMAP4430_CLKSEL_OPP (1 << 0) +#define OMAP4430_CM_DLL_CTRL_DLL_OVERRIDE (1 << 0) +#define OMAP4430_DPLL_SSC_TYPE (1 << 15) +#define OMAP4430_DPLL_SSC_DOWNSPREAD (1 << 14) +#define OMAP4430_DPLL_SSC_ACK (1 << 13) +#define OMAP4430_DPLL_SSC_EN (1 << 12) +#define OMAP4430_DPLL_REGM4XEN (1 << 11) +#define OMAP4430_DPLL_LPMODE_EN (1 << 10) +#define OMAP4430_DPLL_DRIFTGUARD_EN (1 << 3) +#define OMAP4430_DPLL_EN (1 << 0) +#define OMAP4430_DPLL_DCOCLKLDO_PWDN (1 << 4) +#define OMAP4430_AUTO_DPLL_MODE (1 << 0) +#define OMAP4430_DPLL_BYP_CLKSEL (1 << 23) +#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL (1 << 20) +#define OMAP4430_DPLL_MULT (1 << 8) +#define OMAP4430_DPLL_DIV (1 << 0) +#define OMAP4430_DPLL_M2_PWDN (1 << 12) +#define OMAP4430_ST_DPLL_CLKOUT (1 << 9) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_CLKOUT_DIVCHACK (1 << 5) +#define OMAP4430_DPLL_CLKOUT_DIV (1 << 0) +#define OMAP4430_DPLL_M3_PWDN (1 << 12) +#define OMAP4430_ST_DPLL_CLKOUTHIF (1 << 9) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK (1 << 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV (1 << 0) +#define OMAP4430_DELTAMSTEP (1 << 0) +#define OMAP4430_MODFREQDIV_EXPONENT (1 << 8) +#define OMAP4430_MODFREQDIV_MANTISSA (1 << 0) +#define OMAP4430_OVERRIDE_ENABLE (1 << 19) +#define OMAP4430_CORE_DPLL_EMU_MULT (1 << 8) +#define OMAP4430_RESERVED (1 << 7) +#define OMAP4430_CORE_DPLL_EMU_DIV (1 << 0) +#define OMAP4430_ST_DPLL_CLK (1 << 0) +#define OMAP4430_BYPCLK_DPLL_CLKSEL (1 << 0) +#define OMAP4430_DPLL_DCOCLKLDO_PWDN (1 << 4) +#define OMAP4430_ST_DPLL_CLKOUTX2 (1 << 11) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL (1 << 10) +#define OMAP4430_DPLL_DCOCLKLDO_PWDN (1 << 4) +#define OMAP4430_DPLL_DDRPHY_M6_DIV (1 << 24) +#define OMAP4430_DPLL_DDRPHY_M5_DIV (1 << 19) +#define OMAP4430_DPLL_DDRPHY_DPLL_EN (1 << 16) +#define OMAP4430_DPLL_CORE_M2_DIV (1 << 11) +#define OMAP4430_DPLL_CORE_DPLL_EN (1 << 8) +#define OMAP4430_DLL_RESET (1 << 3) +#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_DLL_OVERRIDE (1 << 2) +#define OMAP4430_DPLL_CORE_SYS_REF_CLKSEL (1 << 1) +#define OMAP4430_FREQ_UPDATE (1 << 0) +#define OMAP4430_DPLL_CORE_M5_DIV (1 << 3) +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_CLKSEL_L3 (1 << 2) +#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_CLKSEL_CORE (1 << 1) +#define OMAP4430_GPMC_FREQ_UPDATE (1 << 0) +#define OMAP4430_PRESCAL (1 << 0) +#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK (1 << 13) +#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK (1 << 12) +#define OMAP4430_CLKACTIVITY_ABE_SYSCLK (1 << 11) +#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK (1 << 10) +#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK (1 << 9) +#define OMAP4430_CLKACTIVITY_ABE_X2_CLK (1 << 8) +#define OMAP4430_CLKTRCTRL (1 << 0) +#define OMAP4430_IDLEST (1 << 16) +#define OMAP4430_MODULEMODE (1 << 0) +#define OMAP4430_CLKSEL_AESS_FCLK (1 << 24) +#define OMAP4430_STBYST (1 << 18) +#define OMAP4430_ABE_CLKSEL_INTERNAL_SOURCE (1 << 26) +#define OMAP4430_CLKSEL_SOURCE (1 << 24) +#define OMAP4430_OPTFCLKEN_FCLK2 (1 << 10) +#define OMAP4430_OPTFCLKEN_FCLK1 (1 << 9) +#define OMAP4430_OPTFCLKEN_FCLK0 (1 << 8) +#define OMAP4430_ABE_GPTIMER_CLKCTRL_CLKSEL (1 << 24) +#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK (1 << 8) +#define OMAP4430_D2D_STATDEP (1 << 18) +#define OMAP4430_CEFUSE_STATDEP (1 << 17) +#define OMAP4430_ALWONCORE_STATDEP (1 << 16) +#define OMAP4430_L4WKUP_STATDEP (1 << 15) +#define OMAP4430_L4SEC_STATDEP (1 << 14) +#define OMAP4430_L4PER_STATDEP (1 << 13) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_SDMA_STATDEP (1 << 11) +#define OMAP4430_GFX_STATDEP (1 << 10) +#define OMAP4430_ISS_STATDEP (1 << 9) +#define OMAP4430_DSS_STATDEP (1 << 8) +#define OMAP4430_L3INIT_STATDEP (1 << 7) +#define OMAP4430_L3_2_STATDEP (1 << 6) +#define OMAP4430_L3_1_STATDEP (1 << 5) +#define OMAP4430_MEMIF_STATDEP (1 << 4) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_TESLA_STATDEP (1 << 1) +#define OMAP4430_DUCATI_STATDEP (1 << 0) +#define OMAP4430_WINDOWSIZE (1 << 24) +#define OMAP4430_L3_1_DYNDEP (1 << 5) +#define OMAP4430_MEMIF_DYNDEP (1 << 4) +#define OMAP4430_ABE_DYNDEP (1 << 3) +#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK (1 << 8) +#define OMAP4430_CEFUSE_STATDEP (1 << 17) +#define OMAP4430_ALWONCORE_STATDEP (1 << 16) +#define OMAP4430_L4WKUP_STATDEP (1 << 15) +#define OMAP4430_L4PER_STATDEP (1 << 13) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_ISS_STATDEP (1 << 9) +#define OMAP4430_L3INIT_STATDEP (1 << 7) +#define OMAP4430_L3_2_STATDEP (1 << 6) +#define OMAP4430_L3_1_STATDEP (1 << 5) +#define OMAP4430_MEMIF_STATDEP (1 << 4) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_WINDOWSIZE (1 << 24) +#define OMAP4430_L3_1_DYNDEP (1 << 5) +#define OMAP4430_ABE_DYNDEP (1 << 3) +#define OMAP4430_IVAHD_DYNDEP (1 << 2) +#define OMAP4430_CLKACTIVITY_BGAP_32K_GFCLK (1 << 12) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK (1 << 11) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK (1 << 10) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK (1 << 8) +#define OMAP4430_OPTFCLKEN_BGAP_32K (1 << 8) +#define OMAP4430_REV (1 << 0) + +#endif /* __ARCH_ARM_MACH_OMAP2_CM1_REGBITS_44XX_H */ diff --git a/arch/arm/mach-omap2/cm2-regbits-44xx.h b/arch/arm/mach-omap2/cm2-regbits-44xx.h new file mode 100644 index 0000000..286948d --- /dev/null +++ b/arch/arm/mach-omap2/cm2-regbits-44xx.h @@ -0,0 +1,269 @@ +#ifndef __ARCH_ARM_MACH_OMAP2_CM2_REGBITS_44XX_H +#define __ARCH_ARM_MACH_OMAP2_CM2_REGBITS_44XX_H + +/* + * OMAP4430 Clock Management Module2 register bits + * + * Copyright (C) 2009 Texas Instruments, Inc. + * + * Written by Rajendra Nayak (rnayak@ti.com) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include "cm.h" + +#define OMAP4430_EN_GPT_SHIFT 1 + +#define OMAP4430_CLKACTIVITY_FDIF_GFCLK (1 << 10) +#define OMAP4430_CLKACTIVITY_ISS_GCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK (1 << 8) +#define OMAP4430_CLKTRCTRL (1 << 0) +#define OMAP4430_L3_2_STATDEP (1 << 6) +#define OMAP4430_L3_1_STATDEP (1 << 5) +#define OMAP4430_MEMIF_STATDEP (1 << 4) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_L3_2_DYNDEP (1 << 6) +#define OMAP4430_STBYST (1 << 18) +#define OMAP4430_IDLEST (1 << 16) +#define OMAP4430_OPTFCLKEN_CTRLCLK (1 << 8) +#define OMAP4430_MODULEMODE (1 << 0) +#define OMAP4430_CLKSEL_FCLK (1 << 24) +#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK (1 << 30) +#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK (1 << 29) +#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK (1 << 28) +#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK (1 << 25) +#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK (1 << 24) +#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK (1 << 23) +#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK (1 << 22) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK (1 << 19) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK (1 << 18) +#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK (1 << 17) +#define OMAP4430_CLKACTIVITY_L3INIT_DPLL_ALWON_CLK (1 << 14) +#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK (1 << 13) +#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK (1 << 12) +#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK (1 << 11) +#define OMAP4430_CLKACTIVITY_EMAC_50MHZ_CLK (1 << 10) +#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK (1 << 8) +#define OMAP4430_L4WKUP_STATDEP (1 << 15) +#define OMAP4430_L4SEC_STATDEP (1 << 14) +#define OMAP4430_L4PER_STATDEP (1 << 13) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_L3_1_DYNDEP (1 << 5) +#define OMAP4430_HSMMC1_CLKSEL (1 << 24) +#define OMAP4430_HSMMC2_CLKSEL (1 << 24) +#define OMAP4430_OPTFCLKEN_TXPHYCLK (1 << 8) +#define OMAP4430_CLKSEL_UTMI_P2 (1 << 25) +#define OMAP4430_CLKSEL_UTMI_P1 (1 << 24) +#define OMAP4430_OPTFCLKEN_FUNC48MCLK (1 << 15) +#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK (1 << 10) +#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK (1 << 9) +#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK (1 << 8) +#define OMAP4430_SAR_MODE (1 << 4) +#define OMAP4430_CLKSEL_60M (1 << 24) +#define OMAP4430_OPTFCLKEN_XCLK (1 << 8) +#define OMAP4430_GPTIMER10_CLKSEL (1 << 24) +#define OMAP4430_OPTFCLKEN_PHY_48M (1 << 8) +#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK (1 << 8) +#define OMAP4430_L3_2_STATDEP (1 << 6) +#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK (1 << 10) +#define OMAP4430_CLKACTIVITY_DSS_FCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK (1 << 8) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_OPTFCLKEN_TV_CLK (1 << 11) +#define OMAP4430_OPTFCLKEN_SYS_CLK (1 << 10) +#define OMAP4430_OPTFCLKEN_48MHZ_CLK (1 << 9) +#define OMAP4430_OPTFCLKEN_DSSCLK (1 << 8) +#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK (1 << 25) +#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK (1 << 24) +#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK (1 << 22) +#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK (1 << 21) +#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK (1 << 20) +#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK (1 << 19) +#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK (1 << 18) +#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK (1 << 17) +#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK (1 << 16) +#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK (1 << 15) +#define OMAP4430_CLKACTIVITY_DMT9_GFCLK (1 << 14) +#define OMAP4430_CLKACTIVITY_DMT4_GFCLK (1 << 13) +#define OMAP4430_CLKACTIVITY_DMT3_GFCLK (1 << 12) +#define OMAP4430_CLKACTIVITY_DMT2_GFCLK (1 << 11) +#define OMAP4430_CLKACTIVITY_DMT11_GFCLK (1 << 10) +#define OMAP4430_CLKACTIVITY_DMT10_GFCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_PER_GICLK (1 << 8) +#define OMAP4430_WINDOWSIZE (1 << 24) +#define OMAP4430_L4SEC_DYNDEP (1 << 14) +#define OMAP4430_DSS_DYNDEP (1 << 8) +#define OMAP4430_L3INIT_DYNDEP (1 << 7) +#define OMAP4430_GPTIMER11_CLKSEL (1 << 24) +#define OMAP4430_GPTIMER2_CLKSEL (1 << 24) +#define OMAP4430_GPTIMER3_CLKSEL (1 << 24) +#define OMAP4430_GPTIMER4_CLKSEL (1 << 24) +#define OMAP4430_GPTIMER9_CLKSEL (1 << 24) +#define OMAP4430_OPTFCLKEN_DBCLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DBCLK (1 << 8) +#define OMAP4430_L4PER_CLKSEL_INTERNAL_SOURCE (1 << 25) +#define OMAP4430_CLKSEL_SOURCE (1 << 24) +#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK (1 << 9) +#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK (1 << 8) +#define OMAP4430_CLKACTIVITY_SGX_GFCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK (1 << 8) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_CLKSEL_PER_192M (1 << 25) +#define OMAP4430_CLKSEL_SGX_FCLK (1 << 24) +#define OMAP4430_CLKACTIVITY_L3_1_GICLK (1 << 8) +#define OMAP4430_L4CFG_DYNDEP (1 << 12) +#define OMAP4430_MEMIF_DYNDEP (1 << 4) +#define OMAP4430_ABE_DYNDEP (1 << 3) +#define OMAP4430_CLKACTIVITY_L3_2_GICLK (1 << 8) +#define OMAP4430_L4PER_DYNDEP (1 << 13) +#define OMAP4430_GFX_DYNDEP (1 << 10) +#define OMAP4430_ISS_DYNDEP (1 << 9) +#define OMAP4430_IVAHD_DYNDEP (1 << 2) +#define OMAP4430_DUCATI_DYNDEP (1 << 0) +#define OMAP4430_CLKACTIVITY_DUCATI_GCLK (1 << 8) +#define OMAP4430_CEFUSE_STATDEP (1 << 17) +#define OMAP4430_ALWONCORE_STATDEP (1 << 16) +#define OMAP4430_L4SEC_STATDEP (1 << 14) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_SDMA_STATDEP (1 << 11) +#define OMAP4430_GFX_STATDEP (1 << 10) +#define OMAP4430_ISS_STATDEP (1 << 9) +#define OMAP4430_DSS_STATDEP (1 << 8) +#define OMAP4430_L3INIT_STATDEP (1 << 7) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_IVAHD_STATDEP (1 << 2) +#define OMAP4430_TESLA_STATDEP (1 << 1) +#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK (1 << 8) +#define OMAP4430_L4SEC_STATDEP (1 << 14) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_ISS_STATDEP (1 << 9) +#define OMAP4430_L3INIT_STATDEP (1 << 7) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_DUCATI_STATDEP (1 << 0) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK (1 << 13) +#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK (1 << 12) +#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK (1 << 11) +#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK (1 << 10) +#define OMAP4430_CLKACTIVITY_DLL_CLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK (1 << 8) +#define OMAP4430_OPTFCLKEN_DLL_CLK (1 << 8) +#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK (1 << 8) +#define OMAP4430_L4CFG_STATDEP (1 << 12) +#define OMAP4430_L3INIT_STATDEP (1 << 7) +#define OMAP4430_ABE_STATDEP (1 << 3) +#define OMAP4430_MEMIF_DYNDEP (1 << 4) +#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK (1 << 8) +#define OMAP4430_D2D_DYNDEP (1 << 18) +#define OMAP4430_CEFUSE_DYNDEP (1 << 17) +#define OMAP4430_ALWONCORE_DYNDEP (1 << 16) +#define OMAP4430_L4WKUP_DYNDEP (1 << 15) +#define OMAP4430_SDMA_DYNDEP (1 << 11) +#define OMAP4430_MEMIF_DYNDEP (1 << 4) +#define OMAP4430_TESLA_DYNDEP (1 << 1) +#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK (1 << 8) +#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK (1 << 8) +#define OMAP4430_REV (1 << 0) +#define OMAP4430_CLKSEL_MPU (1 << 0) +#define OMAP4430_CLKSEL_USB (1 << 0) +#define OMAP4430_SCALE_FCLK (1 << 0) +#define OMAP4430_PERF_REQ (1 << 0) +#define OMAP4430_PERF_CURRENT (1 << 0) +#define OMAP4430_DPLL_SSC_TYPE (1 << 15) +#define OMAP4430_DPLL_SSC_DOWNSPREAD (1 << 14) +#define OMAP4430_DPLL_SSC_ACK (1 << 13) +#define OMAP4430_DPLL_SSC_EN (1 << 12) +#define OMAP4430_DPLL_REGM4XEN (1 << 11) +#define OMAP4430_DPLL_LPMODE_EN (1 << 10) +#define OMAP4430_DPLL_DRIFTGUARD_EN (1 << 3) +#define OMAP4430_DPLL_EN (1 << 0) +#define OMAP4430_ST_DPLL_CLK (1 << 0) +#define OMAP4430_DPLL_DCOCLKLDO_PWDN (1 << 4) +#define OMAP4430_AUTO_DPLL_MODE (1 << 0) +#define OMAP4430_DPLL_BYP_CLKSEL (1 << 23) +#define OMAP4430_DPLL_MULT (1 << 8) +#define OMAP4430_DPLL_DIV (1 << 0) +#define OMAP4430_DPLL_M2_PWDN (1 << 12) +#define OMAP4430_ST_DPLL_CLKOUTX2 (1 << 11) +#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL (1 << 10) +#define OMAP4430_ST_DPLL_CLKOUT (1 << 9) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_PER_CLKOUT_DIVCHACK (1 << 5) +#define OMAP4430_DPLL_CLKOUT_DIV (1 << 0) +#define OMAP4430_DPLL_M3_PWDN (1 << 12) +#define OMAP4430_ST_DPLL_CLKOUTHIF (1 << 9) +#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK (1 << 5) +#define OMAP4430_DPLL_CLKOUTHIF_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT1 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT1_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT2 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT2_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT3 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT3_DIV (1 << 0) +#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN (1 << 12) +#define OMAP4430_ST_HSDIVIDER_CLKOUT4 (1 << 9) +#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL (1 << 8) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK (1 << 5) +#define OMAP4430_HSDIVIDER_CLKOUT4_DIV (1 << 0) +#define OMAP4430_DELTAMSTEP (1 << 0) +#define OMAP4430_MODFREQDIV_EXPONENT (1 << 8) +#define OMAP4430_MODFREQDIV_MANTISSA (1 << 0) +#define OMAP4430_OVERRIDE_ENABLE (1 << 19) +#define OMAP4430_PER_DPLL_EMU_MULT (1 << 8) +#define OMAP4430_RESERVED (1 << 7) +#define OMAP4430_PER_DPLL_EMU_DIV (1 << 0) +#define OMAP4430_DPLL_SSC_TYPE (1 << 15) +#define OMAP4430_DPLL_SSC_DOWNSPREAD (1 << 14) +#define OMAP4430_DPLL_SSC_ACK (1 << 13) +#define OMAP4430_DPLL_SSC_EN (1 << 12) +#define OMAP4430_DPLL_DRIFTGUARD_EN (1 << 3) +#define OMAP4430_AUTO_DPLL_MODE (1 << 0) +#define OMAP4430_DPLL_SD_DIV (1 << 24) +#define OMAP4430_DPLL_CLKOUT_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_CLKOUT_DIV (1 << 0) +#define OMAP4430_DELTAMSTEP (1 << 0) +#define OMAP4430_MODFREQDIV_EXPONENT (1 << 8) +#define OMAP4430_MODFREQDIV_MANTISSA (1 << 0) +#define OMAP4430_DPLL_CLKDCOLDO_PWDN (1 << 12) +#define OMAP4430_ST_DPLL_CLKDCOLDO (1 << 9) +#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL (1 << 8) +#define OMAP4430_DPLL_SSC_TYPE (1 << 15) +#define OMAP4430_DPLL_SSC_DOWNSPREAD (1 << 14) +#define OMAP4430_DPLL_SSC_ACK (1 << 13) +#define OMAP4430_DPLL_SSC_EN (1 << 12) +#define OMAP4430_DPLL_REGM4XEN (1 << 11) +#define OMAP4430_DPLL_LPMODE_EN (1 << 10) +#define OMAP4430_DPLL_DRIFTGUARD_EN (1 << 3) +#define OMAP4430_AUTO_DPLL_MODE (1 << 0) +#define OMAP4430_DPLL_CLKOUT_DIV (1 << 0) +#define OMAP4430_DELTAMSTEP (1 << 0) +#define OMAP4430_MODFREQDIV_EXPONENT (1 << 8) +#define OMAP4430_MODFREQDIV_MANTISSA (1 << 0) +#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK (1 << 11) +#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK (1 << 10) +#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK (1 << 9) +#define OMAP4430_CLKACTIVITY_L4_AO_ICLK (1 << 8) + +#endif /* __ARCH_ARM_MACH_OMAP2_CM2_REGBITS_44XX_H */

[v2,5/6] ARM: OMAP4: PM: Adds CM1/2 register defs for OMAP4

Commit Message

Comments

Patch