From patchwork Tue May 6 13:33:52 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 4121871 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 5E8C1BFF02 for ; Tue, 6 May 2014 13:42:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 58106201EC for ; Tue, 6 May 2014 13:42:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 458A9201CE for ; Tue, 6 May 2014 13:42:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757544AbaEFNfV (ORCPT ); Tue, 6 May 2014 09:35:21 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:54842 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752167AbaEFNfR (ORCPT ); Tue, 6 May 2014 09:35:17 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s46DYqr6022574; Tue, 6 May 2014 08:34:52 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s46DYpOS031907; Tue, 6 May 2014 08:34:51 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 6 May 2014 08:34:51 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s46DYE8V031249; Tue, 6 May 2014 08:34:48 -0500 From: Kishon Vijay Abraham I To: , , , , , CC: , , Kishon Vijay Abraham I , Bjorn Helgaas , Marek Vasut Subject: [PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU Date: Tue, 6 May 2014 19:03:52 +0530 Message-ID: <1399383244-14556-7-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1399383244-14556-1-git-send-email-kishon@ti.com> References: <1399383244-14556-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit address. So whenever the cpu issues a read/write request, the 4 most significant bits are used by L3 to determine the target controller. For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming the outbound translation window the *base* should be programmed as 0x000_0000. Whenever we try to write to say 0x2000_0000, it will be translated to whatever we have programmed in the translation window with base as 0x000_0000. Cc: Bjorn Helgaas Cc: Marek Vasut Signed-off-by: Kishon Vijay Abraham I Acked-by: Jingoo Han Acked-by: Mohit Kumar --- .../devicetree/bindings/pci/designware-pcie.txt | 1 + drivers/pci/host/pcie-designware.c | 39 ++++++++++++++------ drivers/pci/host/pcie-designware.h | 1 + 3 files changed, 29 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index d6fae13..c574dd3 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -27,6 +27,7 @@ Optional properties for fsl,imx6q-pcie - power-on-gpio: gpio pin number of power-enable signal - wake-up-gpio: gpio pin number of incoming wakeup signal - disable-gpio: gpio pin number of outgoing rfkill/endpoint disable signal +- base-mask: address mask for the PCIe controller target port Example: diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index c4e3732..243f148 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -463,6 +463,9 @@ int __init dw_pcie_host_init(struct pcie_port *pp) return -EINVAL; } + if (of_property_read_u64(np, "base-mask", &pp->base_mask)) + pp->base_mask = ~0x0ULL; + if (IS_ENABLED(CONFIG_PCI_MSI)) { pp->irq_domain = irq_domain_add_linear(pp->dev->of_node, MAX_MSI_IRQS, &msi_domain_ops, @@ -502,12 +505,15 @@ int __init dw_pcie_host_init(struct pcie_port *pp) static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) { + u64 cfg0_base; + + cfg0_base = pp->cfg0_base & pp->base_mask; /* Program viewport 0 : OUTBOUND : CFG0 */ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, PCIE_ATU_VIEWPORT); - dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE); - dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE); - dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1, + dw_pcie_writel_rc(pp, cfg0_base, PCIE_ATU_LOWER_BASE); + dw_pcie_writel_rc(pp, (cfg0_base >> 32), PCIE_ATU_UPPER_BASE); + dw_pcie_writel_rc(pp, cfg0_base + pp->config.cfg0_size - 1, PCIE_ATU_LIMIT); dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); @@ -517,13 +523,16 @@ static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev) static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) { + u64 cfg1_base; + + cfg1_base = pp->cfg1_base & pp->base_mask; /* Program viewport 1 : OUTBOUND : CFG1 */ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE); - dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE); - dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1, + dw_pcie_writel_rc(pp, cfg1_base, PCIE_ATU_LOWER_BASE); + dw_pcie_writel_rc(pp, (cfg1_base >> 32), PCIE_ATU_UPPER_BASE); + dw_pcie_writel_rc(pp, cfg1_base + pp->config.cfg1_size - 1, PCIE_ATU_LIMIT); dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); @@ -532,13 +541,16 @@ static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) { + u64 mem_base; + + mem_base = pp->mem_base & pp->base_mask; /* Program viewport 0 : OUTBOUND : MEM */ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); - dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); - dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, + dw_pcie_writel_rc(pp, mem_base, PCIE_ATU_LOWER_BASE); + dw_pcie_writel_rc(pp, (mem_base >> 32), PCIE_ATU_UPPER_BASE); + dw_pcie_writel_rc(pp, mem_base + pp->config.mem_size - 1, PCIE_ATU_LIMIT); dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), @@ -548,13 +560,16 @@ static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) { + u64 io_base; + + io_base = pp->io_base & pp->base_mask; /* Program viewport 1 : OUTBOUND : IO */ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, PCIE_ATU_VIEWPORT); dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); - dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); - dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); - dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, + dw_pcie_writel_rc(pp, io_base, PCIE_ATU_LOWER_BASE); + dw_pcie_writel_rc(pp, (io_base >> 32), PCIE_ATU_UPPER_BASE); + dw_pcie_writel_rc(pp, io_base + pp->config.io_size - 1, PCIE_ATU_LIMIT); dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index 3063b35..3fa12a6 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -35,6 +35,7 @@ struct pcie_port { struct device *dev; u8 root_bus_nr; void __iomem *dbi_base; + u64 base_mask; u64 cfg0_base; void __iomem *va_cfg0_base; u64 cfg1_base;