| Message ID | 1400831485-28576-8-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, El 23/05/14 04:51, Chen-Yu Tsai escribió: > The N factor for PLL6 counts from 1 to 32, as specified in the A23 > manual, and shown in Allwinner's original code. Are you sure about this? The A23 manual I'm looking at has a 5-bit field (so 0-31) on 12:8, and the examples count from 0 (eg Factor=0 N=1 ... Factor=31 N=32). Cheers, Emilio
Hi, On Fri, May 23, 2014 at 9:09 PM, Emilio López <emilio@elopez.com.ar> wrote: > Hi, > > El 23/05/14 04:51, Chen-Yu Tsai escribió: > >> The N factor for PLL6 counts from 1 to 32, as specified in the A23 >> manual, and shown in Allwinner's original code. > > > Are you sure about this? The A23 manual I'm looking at has a 5-bit field (so > 0-31) on 12:8, and the examples count from 0 (eg Factor=0 N=1 ... Factor=31 > N=32). From the A23 manual: Factor = 0, N = 1 Factor = 1, N = 2 Factor = 2, N = 3 and so on From the A20 manual: Factor = 0, N = 0 Factor = 1, N = 1 Factor = 2, N = 2 The "N factor" I referred to in my commit message is the N used in the calculation, not what is stored in the bit field. Hope this makes it clear. :) Cheers ChenYu
On Fri, May 23, 2014 at 03:51:10PM +0800, Chen-Yu Tsai wrote: > The N factor for PLL6 counts from 1 to 32, as specified in the A23 > manual, and shown in Allwinner's original code. > > This patch fixes the N factor in the clock driver, as well as the > comment describing it. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Thanks, Maxime
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c index b2c6d12..6500a1b 100644 --- a/drivers/clk/sunxi/clk-sunxi.c +++ b/drivers/clk/sunxi/clk-sunxi.c @@ -198,7 +198,7 @@ static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate, /** * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6 * PLL6 rate is calculated as follows - * rate = parent_rate * n * (k + 1) / 2 + * rate = parent_rate * (n + 1) * (k + 1) / 2 * parent_rate is always 24Mhz */ @@ -225,7 +225,7 @@ static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate, if (*k > 3) *k = 3; - *n = DIV_ROUND_UP(div, (*k+1)); + *n = DIV_ROUND_UP(div, (*k+1)) - 1; } /** @@ -434,6 +434,7 @@ static struct clk_factors_config sun6i_a31_pll6_config = { .nwidth = 5, .kshift = 4, .kwidth = 2, + .n_from_one = 1, }; static struct clk_factors_config sun4i_apb1_config = {
The N factor for PLL6 counts from 1 to 32, as specified in the A23 manual, and shown in Allwinner's original code. This patch fixes the N factor in the clock driver, as well as the comment describing it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- drivers/clk/sunxi/clk-sunxi.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)