From patchwork Thu May 29 06:38:14 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 4261751 X-Patchwork-Delegate: bhelgaas@google.com Return-Path: X-Original-To: patchwork-linux-pci@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 2F250BF90B for ; Thu, 29 May 2014 06:42:59 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 5331C2034A for ; Thu, 29 May 2014 06:42:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6C113202E5 for ; Thu, 29 May 2014 06:42:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933256AbaE2GkS (ORCPT ); Thu, 29 May 2014 02:40:18 -0400 Received: from bear.ext.ti.com ([192.94.94.41]:59903 "EHLO bear.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932739AbaE2GkP (ORCPT ); Thu, 29 May 2014 02:40:15 -0400 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by bear.ext.ti.com (8.13.7/8.13.7) with ESMTP id s4T6dcDA004701; Thu, 29 May 2014 01:39:38 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4T6dcjl008630; Thu, 29 May 2014 01:39:38 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Thu, 29 May 2014 01:39:37 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id s4T6cgHZ022845; Thu, 29 May 2014 01:39:33 -0500 From: Kishon Vijay Abraham I To: , , , , , CC: , , , , Rajendra Nayak , Tero Kristo , Paul Walmsley , Rob Herring , Pawel Moll , Mark Rutland , Kumar Gala , Keerthy Subject: [PATCH v2 12/18] ARM: dts: dra7xx-clocks: rename pcie clocks to accommodate second PHY instance Date: Thu, 29 May 2014 12:08:14 +0530 Message-ID: <1401345500-20188-13-git-send-email-kishon@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1401345500-20188-1-git-send-email-kishon@ti.com> References: <1401345500-20188-1-git-send-email-kishon@ti.com> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org X-Spam-Status: No, score=-7.5 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP There are two instances of PCIe PHY in DRA7xx. So renamed optfclk_pciephy_32khz, optfclk_pciephy_clk and optfclk_pciephy_div_clk to optfclk_pciephy1_32khz, optfclk_pciephy1_clk and optfclk_pciephy1_div_clk respectively. This is needed for adding the clocks for second PCIe PHY instance. Cc: Rajendra Nayak Cc: Tero Kristo Cc: Paul Walmsley Cc: Tony Lindgren Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Kumar Gala Signed-off-by: Keerthy Signed-off-by: Kishon Vijay Abraham I --- arch/arm/boot/dts/dra7xx-clocks.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index e1bd052..3d8c9c2 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1165,7 +1165,7 @@ reg = <0x021c>, <0x0220>; }; - optfclk_pciephy_32khz: optfclk_pciephy_32khz@4a0093b0 { + optfclk_pciephy1_32khz: optfclk_pciephy_32khz@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&sys_32k_ck>; #clock-cells = <0>; @@ -1183,7 +1183,7 @@ ti,max-div = <2>; }; - optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { + optfclk_pciephy1_clk: optfclk_pciephy_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&apll_pcie_ck>; #clock-cells = <0>; @@ -1191,7 +1191,7 @@ ti,bit-shift = <9>; }; - optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { + optfclk_pciephy1_div_clk: optfclk_pciephy_div_clk@4a0093b0 { compatible = "ti,gate-clock"; clocks = <&optfclk_pciephy_div>; #clock-cells = <0>;