| Message ID | 1401345500-20188-7-git-send-email-kishon@ti.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: > From: Keerthy <j-keerthy@ti.com> > > Add divider table to optfclk_pciephy_div clock. The Documentation > for divider clock can be found at ../clock/ti/divider.txt This patch requires a better changelog. Why is the change done, any TRM refs etc.? -Tero > > Cc: Rajendra Nayak <rnayak@ti.com> > Cc: Tero Kristo <t-kristo@ti.com> > Cc: Paul Walmsley <paul@pwsan.com> > Signed-off-by: Keerthy <j-keerthy@ti.com> > Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi > index c767687..55e95c5 100644 > --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi > +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi > @@ -1170,6 +1170,7 @@ > clocks = <&apll_pcie_ck>; > #clock-cells = <0>; > reg = <0x021c>; > + ti,dividers = <2>, <1>; > ti,bit-shift = <8>; > ti,max-div = <2>; > }; > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Hi Tero, On Thursday 19 June 2014 04:40 PM, Tero Kristo wrote: > On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >> From: Keerthy <j-keerthy@ti.com> >> >> Add divider table to optfclk_pciephy_div clock. The Documentation >> for divider clock can be found at ../clock/ti/divider.txt > > This patch requires a better changelog. Why is the change done, any TRM refs etc.? The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 based on if the divider value is 0x2 or 0x1. Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the block diagram of Clock Generator Subsystem of PCIe PHY module. We have to do a bypass (divided by 1) in order to get the correct PCIE_PHY_DIV_GCLK frequency. Thanks Kishon > > -Tero > >> >> Cc: Rajendra Nayak <rnayak@ti.com> >> Cc: Tero Kristo <t-kristo@ti.com> >> Cc: Paul Walmsley <paul@pwsan.com> >> Signed-off-by: Keerthy <j-keerthy@ti.com> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index c767687..55e95c5 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -1170,6 +1170,7 @@ >> clocks = <&apll_pcie_ck>; >> #clock-cells = <0>; >> reg = <0x021c>; >> + ti,dividers = <2>, <1>; >> ti,bit-shift = <8>; >> ti,max-div = <2>; >> }; >> > -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/19/2014 03:45 PM, Kishon Vijay Abraham I wrote: > Hi Tero, > > On Thursday 19 June 2014 04:40 PM, Tero Kristo wrote: >> On 05/29/2014 09:38 AM, Kishon Vijay Abraham I wrote: >>> From: Keerthy <j-keerthy@ti.com> >>> >>> Add divider table to optfclk_pciephy_div clock. The Documentation >>> for divider clock can be found at ../clock/ti/divider.txt >> >> This patch requires a better changelog. Why is the change done, any TRM refs etc.? > > The 8th bit of CM_CLKMODE_APLL_PCIE can be programmed to either 0x0 or 0x1 > based on if the divider value is 0x2 or 0x1. > > Figure 26-21. PCIe PHY Clock Generator Overview in vE of DRA7xx ES1.0 shows the > block diagram of Clock Generator Subsystem of PCIe PHY module. We have to do a > bypass (divided by 1) in order to get the correct PCIE_PHY_DIV_GCLK Yes, something like this on the changelog would be good. -Tero > frequency. > > Thanks > Kishon >> >> -Tero >> >>> >>> Cc: Rajendra Nayak <rnayak@ti.com> >>> Cc: Tero Kristo <t-kristo@ti.com> >>> Cc: Paul Walmsley <paul@pwsan.com> >>> Signed-off-by: Keerthy <j-keerthy@ti.com> >>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> >>> --- >>> arch/arm/boot/dts/dra7xx-clocks.dtsi | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> index c767687..55e95c5 100644 >>> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >>> @@ -1170,6 +1170,7 @@ >>> clocks = <&apll_pcie_ck>; >>> #clock-cells = <0>; >>> reg = <0x021c>; >>> + ti,dividers = <2>, <1>; >>> ti,bit-shift = <8>; >>> ti,max-div = <2>; >>> }; >>> >> -- To unsubscribe from this list: send the line "unsubscribe linux-omap" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi index c767687..55e95c5 100644 --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi @@ -1170,6 +1170,7 @@ clocks = <&apll_pcie_ck>; #clock-cells = <0>; reg = <0x021c>; + ti,dividers = <2>, <1>; ti,bit-shift = <8>; ti,max-div = <2>; };