| Message ID | 1406786498-3935-1-git-send-email-addy.ke@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Best Regards, Jaehoon Chung On 07/31/2014 03:01 PM, Addy Ke wrote: > This patch focuses on clock setting for RK3288 mmc controller. > > In RK3288 mmc controller, CLKDIV register can only be set 0 or 1, > and if DDR 8bit mode, CLKDIV register must be set 1. > > Reported-by Doug Anderson <dianders@chromium.org> > Suggested-by: Jaehoon Chung <jh80.chung@samsung.com> > Suggested-by: Doug Anderson <dianders@chromium.org> > Signed-off-by: Addy Ke <addy.ke@rock-chips.com> > --- > changes since v1: > - dw_mci_rk3288_setup_clock: do not call clk_get_rate(), just use the > host->bus_hz which is already called by dw_mmc.c, suggested by Jaehoon Chung > > changes since v2: > - merge from ChromiumOS tree, fix up clock settting bug, > which cause DDR50 mode for emmc not to work, reported by Doug Anderson > - remove MMC_TIMING_UHS_DDR50 condition, because on RK3288 only emmc can work > in 8bit mode, suggested by Doug Anderson > > .../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 6 ++- > drivers/mmc/host/dw_mmc-pltfm.c | 56 +++++++++++++++++++++- > 2 files changed, 58 insertions(+), 4 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt > index c559f3f..c327c2d 100644 > --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt > +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt > @@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller. > Required Properties: > > * compatible: should be > - - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following > + - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, > + before RK3288 > + - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 > > Example: > > rkdwmmc0@12200000 { > - compatible = "rockchip,rk2928-dw-mshc"; > + compatible = "rockchip,rk3288-dw-mshc"; > reg = <0x12200000 0x1000>; > interrupts = <0 75 0>; > #address-cells = <1>; > diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c > index d4a47a9..b547f7a 100644 > --- a/drivers/mmc/host/dw_mmc-pltfm.c > +++ b/drivers/mmc/host/dw_mmc-pltfm.c > @@ -21,17 +21,67 @@ > #include <linux/mmc/mmc.h> > #include <linux/mmc/dw_mmc.h> > #include <linux/of.h> > +#include <linux/clk.h> > > #include "dw_mmc.h" > #include "dw_mmc-pltfm.h" > > +#define RK3288_CLKGEN_DIV 2 > + > static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr) > { > *cmdr |= SDMMC_CMD_USE_HOLD_REG; > } > > -static const struct dw_mci_drv_data rockchip_drv_data = { > +static int dw_mci_rk3288_setup_clock(struct dw_mci *host) > +{ > + host->bus_hz /= RK3288_CLKGEN_DIV; > + > + return 0; > +} > + > +static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) > +{ > + int ret; > + unsigned int cclkin; > + u32 bus_hz; > + > + /* > + * cclkin: source clock of mmc controller. > + * bus_hz: card interface clock generated by CLKGEN. > + * bus_hz = cclkin / RK3288_CLKGEN_DIV; > + * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) > + * > + * Note: div can only be 0 or 1 > + * if DDR50 8bit mode(only emmc work in 8bit mode), > + * div must be set 1 > + */ > + if ((ios->bus_width == MMC_BUS_WIDTH_8) && > + (ios->timing == MMC_TIMING_MMC_DDR52)) > + cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; > + else > + cclkin = ios->clock * RK3288_CLKGEN_DIV; > + > + ret = clk_set_rate(host->ciu_clk, cclkin); > + if (ret) > + dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); > + > + bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; > + if (bus_hz != host->bus_hz) { > + host->bus_hz = bus_hz; > + /* force dw_mci_setup_bus() */ > + host->current_speed = 0; > + } > +} > + > +static const struct dw_mci_drv_data rk2928_drv_data = { > + .prepare_command = dw_mci_pltfm_prepare_command, > +}; > + > +static const struct dw_mci_drv_data rk3288_drv_data = { > .prepare_command = dw_mci_pltfm_prepare_command, > + .set_ios = dw_mci_rk3288_set_ios, > + .setup_clock = dw_mci_rk3288_setup_clock, > }; > > static const struct dw_mci_drv_data socfpga_drv_data = { > @@ -95,7 +145,9 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); > static const struct of_device_id dw_mci_pltfm_match[] = { > { .compatible = "snps,dw-mshc", }, > { .compatible = "rockchip,rk2928-dw-mshc", > - .data = &rockchip_drv_data }, > + .data = &rk2928_drv_data }, > + { .compatible = "rockchip,rk3288-dw-mshc", > + .data = &rk3288_drv_data }, > { .compatible = "altr,socfpga-dw-mshc", > .data = &socfpga_drv_data }, > {}, > -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt index c559f3f..c327c2d 100644 --- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt @@ -10,12 +10,14 @@ extensions to the Synopsys Designware Mobile Storage Host Controller. Required Properties: * compatible: should be - - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following + - "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following, + before RK3288 + - "rockchip,rk3288-dw-mshc": for Rockchip RK3288 Example: rkdwmmc0@12200000 { - compatible = "rockchip,rk2928-dw-mshc"; + compatible = "rockchip,rk3288-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>; diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index d4a47a9..b547f7a 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -21,17 +21,67 @@ #include <linux/mmc/mmc.h> #include <linux/mmc/dw_mmc.h> #include <linux/of.h> +#include <linux/clk.h> #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define RK3288_CLKGEN_DIV 2 + static void dw_mci_pltfm_prepare_command(struct dw_mci *host, u32 *cmdr) { *cmdr |= SDMMC_CMD_USE_HOLD_REG; } -static const struct dw_mci_drv_data rockchip_drv_data = { +static int dw_mci_rk3288_setup_clock(struct dw_mci *host) +{ + host->bus_hz /= RK3288_CLKGEN_DIV; + + return 0; +} + +static void dw_mci_rk3288_set_ios(struct dw_mci *host, struct mmc_ios *ios) +{ + int ret; + unsigned int cclkin; + u32 bus_hz; + + /* + * cclkin: source clock of mmc controller. + * bus_hz: card interface clock generated by CLKGEN. + * bus_hz = cclkin / RK3288_CLKGEN_DIV; + * ios->clock = (div == 0) ? bus_hz : (bus_hz / (2 * div)) + * + * Note: div can only be 0 or 1 + * if DDR50 8bit mode(only emmc work in 8bit mode), + * div must be set 1 + */ + if ((ios->bus_width == MMC_BUS_WIDTH_8) && + (ios->timing == MMC_TIMING_MMC_DDR52)) + cclkin = 2 * ios->clock * RK3288_CLKGEN_DIV; + else + cclkin = ios->clock * RK3288_CLKGEN_DIV; + + ret = clk_set_rate(host->ciu_clk, cclkin); + if (ret) + dev_warn(host->dev, "failed to set rate %uHz\n", ios->clock); + + bus_hz = clk_get_rate(host->ciu_clk) / RK3288_CLKGEN_DIV; + if (bus_hz != host->bus_hz) { + host->bus_hz = bus_hz; + /* force dw_mci_setup_bus() */ + host->current_speed = 0; + } +} + +static const struct dw_mci_drv_data rk2928_drv_data = { + .prepare_command = dw_mci_pltfm_prepare_command, +}; + +static const struct dw_mci_drv_data rk3288_drv_data = { .prepare_command = dw_mci_pltfm_prepare_command, + .set_ios = dw_mci_rk3288_set_ios, + .setup_clock = dw_mci_rk3288_setup_clock, }; static const struct dw_mci_drv_data socfpga_drv_data = { @@ -95,7 +145,9 @@ EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, { .compatible = "rockchip,rk2928-dw-mshc", - .data = &rockchip_drv_data }, + .data = &rk2928_drv_data }, + { .compatible = "rockchip,rk3288-dw-mshc", + .data = &rk3288_drv_data }, { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data }, {},
This patch focuses on clock setting for RK3288 mmc controller. In RK3288 mmc controller, CLKDIV register can only be set 0 or 1, and if DDR 8bit mode, CLKDIV register must be set 1. Reported-by Doug Anderson <dianders@chromium.org> Suggested-by: Jaehoon Chung <jh80.chung@samsung.com> Suggested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Addy Ke <addy.ke@rock-chips.com> --- changes since v1: - dw_mci_rk3288_setup_clock: do not call clk_get_rate(), just use the host->bus_hz which is already called by dw_mmc.c, suggested by Jaehoon Chung changes since v2: - merge from ChromiumOS tree, fix up clock settting bug, which cause DDR50 mode for emmc not to work, reported by Doug Anderson - remove MMC_TIMING_UHS_DDR50 condition, because on RK3288 only emmc can work in 8bit mode, suggested by Doug Anderson .../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 6 ++- drivers/mmc/host/dw_mmc-pltfm.c | 56 +++++++++++++++++++++- 2 files changed, 58 insertions(+), 4 deletions(-)