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[1/2] r600g/radeonsi: Reduce or even drop special treatment of persistent mappings

Message ID 1406799831-2502-4-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer July 31, 2014, 9:43 a.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---
 src/gallium/drivers/radeon/r600_buffer_common.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

Comments

Marek Olšák July 31, 2014, 5:36 p.m. UTC | #1 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Marek

On Thu, Jul 31, 2014 at 11:43 AM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
> ---
>  src/gallium/drivers/radeon/r600_buffer_common.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
> index 4e6b897..154c33d 100644
> --- a/src/gallium/drivers/radeon/r600_buffer_common.c
> +++ b/src/gallium/drivers/radeon/r600_buffer_common.c
> @@ -127,13 +127,17 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
>                 break;
>         }
>
> -       /* Use GTT for all persistent mappings, because they are
> -        * always cached and coherent. */
> -       if (res->b.b.target == PIPE_BUFFER &&
> +       /* Use GTT for all persistent mappings with older kernels, because they
> +        * didn't always flush the HDP cache before CS execution.
> +        *
> +        * Write-combined CPU mappings are fine, the kernel ensures all CPU
> +        * writes finish before the GPU executes a command stream.
> +        */
> +       if (rscreen->info.drm_minor < 40 &&
> +           res->b.b.target == PIPE_BUFFER &&
>             res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
>                               PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
>                 res->domains = RADEON_DOMAIN_GTT;
> -               flags = 0;
>         }
>
>         /* Tiled textures are unmappable. Always put them in VRAM. */
> --
> 2.0.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 4e6b897..154c33d 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -127,13 +127,17 @@  bool r600_init_resource(struct r600_common_screen *rscreen,
 		break;
 	}
 
-	/* Use GTT for all persistent mappings, because they are
-	 * always cached and coherent. */
-	if (res->b.b.target == PIPE_BUFFER &&
+	/* Use GTT for all persistent mappings with older kernels, because they
+	 * didn't always flush the HDP cache before CS execution.
+	 *
+	 * Write-combined CPU mappings are fine, the kernel ensures all CPU
+	 * writes finish before the GPU executes a command stream.
+	 */
+	if (rscreen->info.drm_minor < 40 &&
+	    res->b.b.target == PIPE_BUFFER &&
 	    res->b.b.flags & (PIPE_RESOURCE_FLAG_MAP_PERSISTENT |
 			      PIPE_RESOURCE_FLAG_MAP_COHERENT)) {
 		res->domains = RADEON_DOMAIN_GTT;
-		flags = 0;
 	}
 
 	/* Tiled textures are unmappable. Always put them in VRAM. */