From patchwork Mon Aug 18 08:56:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiubo Li X-Patchwork-Id: 4733971 Return-Path: X-Original-To: patchwork-alsa-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id D09E69F344 for ; Mon, 18 Aug 2014 09:01:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id AC1472011E for ; Mon, 18 Aug 2014 09:01:49 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) by mail.kernel.org (Postfix) with ESMTP id 1990E200DE for ; Mon, 18 Aug 2014 09:01:48 +0000 (UTC) Received: by alsa0.perex.cz (Postfix, from userid 1000) id 175B0265530; Mon, 18 Aug 2014 11:01:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 Received: from alsa0.perex.cz (localhost [IPv6:::1]) by alsa0.perex.cz (Postfix) with ESMTP id 2C4A92654DC; Mon, 18 Aug 2014 11:01:36 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id 8C8B42654E0; Mon, 18 Aug 2014 11:01:34 +0200 (CEST) Received: from na01-bl2-obe.outbound.protection.outlook.com (mail-bl2lp0205.outbound.protection.outlook.com [207.46.163.205]) by alsa0.perex.cz (Postfix) with ESMTP id 99EC12654BD for ; Mon, 18 Aug 2014 11:01:27 +0200 (CEST) Received: from BLUPR03CA009.namprd03.prod.outlook.com (10.255.124.26) by BY2PR0301MB0613.namprd03.prod.outlook.com (25.160.125.23) with Microsoft SMTP Server (TLS) id 15.0.1005.10; Mon, 18 Aug 2014 09:01:12 +0000 Received: from BL2FFO11FD010.protection.gbl (207.46.163.212) by BLUPR03CA009.outlook.office365.com (10.255.124.26) with Microsoft SMTP Server (TLS) id 15.0.1010.13 via Frontend Transport; Mon, 18 Aug 2014 09:01:11 +0000 Received: from tx30smr01.am.freescale.net (192.88.168.50) by BL2FFO11FD010.mail.protection.outlook.com (10.173.161.16) with Microsoft SMTP Server (TLS) id 15.0.1010.11 via Frontend Transport; Mon, 18 Aug 2014 09:01:11 +0000 Received: from titan.ap.freescale.net ([10.192.208.233]) by tx30smr01.am.freescale.net (8.14.3/8.14.0) with ESMTP id s7I914Bq014090; Mon, 18 Aug 2014 02:01:05 -0700 From: Xiubo Li To: , , , , , Date: Mon, 18 Aug 2014 16:56:55 +0800 Message-ID: <1408352215-12014-1-git-send-email-Li.Xiubo@freescale.com> X-Mailer: git-send-email 1.8.5 X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:192.88.168.50; CTRY:US; IPV:CAL; IPV:NLI; EFV:NLI; SFV:NSPM; SFS:(10019005)(6009001)(189002)(199003)(99396002)(84676001)(36756003)(81342001)(104016003)(86362001)(68736004)(104166001)(77156001)(93916002)(50986999)(31966008)(15975445006)(26826002)(21056001)(102836001)(74502001)(74662001)(81542001)(19580395003)(88136002)(19580405001)(83322001)(87936001)(89996001)(77982001)(79102001)(50226001)(92726001)(4396001)(92566001)(76482001)(83072002)(2201001)(62966002)(85852003)(64706001)(107046002)(50466002)(46102001)(47776003)(80022001)(87286001)(85306004)(97736001)(6806004)(20776003)(106466001)(229853001)(105606002)(95666004)(44976005)(48376002); DIR:OUT; SFP:1102; SCL:1; SRVR:BY2PR0301MB0613; H:tx30smr01.am.freescale.net; FPR:; MLV:ovrnspm; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; MIME-Version: 1.0 X-Microsoft-Antispam: BCL:0;PCL:0;RULEID:;UriScan:; X-Forefront-PRVS: 03077579FF Received-SPF: Fail (protection.outlook.com: domain of freescale.com does not designate 192.88.168.50 as permitted sender) receiver=protection.outlook.com; client-ip=192.88.168.50; helo=tx30smr01.am.freescale.net; Authentication-Results: spf=fail (sender IP is 192.88.168.50) smtp.mailfrom=Li.Xiubo@freescale.com; X-OriginatorOrg: freescale.com Cc: devicetree@vger.kernel.org, Xiubo Li Subject: [alsa-devel] [PATCH] ASoC: fsl-asrc: Convert to use regmap framework's endianness method. X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Xiubo Li Reviewed-by: Varka Bhadram --- This is depended on the following regmap framework patches, which have just been merged into linux-next tree: https://lkml.org/lkml/2014/7/15/6 https://lkml.org/lkml/2014/7/15/5 https://lkml.org/lkml/2014/7/15/7 Documentation/devicetree/bindings/sound/fsl,asrc.txt | 10 +++++++--- sound/soc/fsl/fsl_asrc.c | 6 +----- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index b93362a..791f372 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -26,9 +26,12 @@ Required properties: "ipg" Peripheral clock to driver module. "asrck_<0-f>" Clock sources for input and output clock. - - big-endian : If this property is absent, the little endian mode - will be in use as default. Otherwise, the big endian - mode will be in use for all the device registers. + - big-endian : If this property is absent, the native endian mode + (same with CPU) will be in use as default. Otherwise, + the big endian mode will be in use for all the device + registers. + See Documentation/devicetree/bindings/regmap/regmap.txt + for more detail. - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. @@ -56,5 +59,6 @@ asrc: asrc@02034000 { "txa", "txb", "txc"; fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; + big-endian; status = "okay"; }; diff --git a/sound/soc/fsl/fsl_asrc.c b/sound/soc/fsl/fsl_asrc.c index 8221104..3b14531 100644 --- a/sound/soc/fsl/fsl_asrc.c +++ b/sound/soc/fsl/fsl_asrc.c @@ -684,7 +684,7 @@ static bool fsl_asrc_writeable_reg(struct device *dev, unsigned int reg) } } -static struct regmap_config fsl_asrc_regmap_config = { +static const struct regmap_config fsl_asrc_regmap_config = { .reg_bits = 32, .reg_stride = 4, .val_bits = 32, @@ -802,10 +802,6 @@ static int fsl_asrc_probe(struct platform_device *pdev) asrc_priv->paddr = res->start; - /* Register regmap and let it prepare core clock */ - if (of_property_read_bool(np, "big-endian")) - fsl_asrc_regmap_config.val_format_endian = REGMAP_ENDIAN_BIG; - asrc_priv->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "mem", regs, &fsl_asrc_regmap_config); if (IS_ERR(asrc_priv->regmap)) {