| Message ID | 1411311493-24344-4-git-send-email-wens@csie.org (mailing list archive) |
|---|---|
| State | New, archived |
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Hi, Thanks, a lot for your patches :) On Sun, Sep 21, 2014 at 10:58:10PM +0800, Chen-Yu Tsai wrote: > The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and > 4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core > PowerVR G6230 GPU. > > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > arch/arm/boot/dts/sun9i-a80.dtsi | 280 +++++++++++++++++++++++++++++++++++++++ > 1 file changed, 280 insertions(+) > create mode 100644 arch/arm/boot/dts/sun9i-a80.dtsi > > diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi > new file mode 100644 > index 0000000..f23ea59 > --- /dev/null > +++ b/arch/arm/boot/dts/sun9i-a80.dtsi > @@ -0,0 +1,280 @@ > +/* > + * Copyright 2014 Chen-Yu Tsai > + * > + * Chen-Yu Tsai <wens@csie.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPL or the X11 license, at your option. Note that this dual > + * licensing only applies to this file, and not this project as a > + * whole. > + * > + * a) This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of the > + * License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public > + * License along with this library; if not, write to the Free > + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, > + * MA 02110-1301 USA > + * > + * Or, alternatively, > + * > + * b) Permission is hereby granted, free of charge, to any person > + * obtaining a copy of this software and associated documentation > + * files (the "Software"), to deal in the Software without > + * restriction, including without limitation the rights to use, > + * copy, modify, merge, publish, distribute, sublicense, and/or > + * sell copies of the Software, and to permit persons to whom the > + * Software is furnished to do so, subject to the following > + * conditions: > + * > + * The above copyright notice and this permission notice shall be > + * included in all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR > + * OTHER DEALINGS IN THE SOFTWARE. > + */ > + > +/include/ "skeleton.dtsi" > + > +/ { > + interrupt-parent = <&gic>; > + > + aliases { > + serial0 = &uart0; > + serial1 = &uart1; > + serial2 = &uart2; > + serial3 = &uart3; > + serial4 = &uart4; > + serial5 = &uart5; > + serial6 = &r_uart; > + }; > + > + cpu-map { > + cluster0 { > + core0 { > + cpu = <&cpu0>; > + }; > + core1 { > + cpu = <&cpu1>; > + }; > + core2 { > + cpu = <&cpu2>; > + }; > + core3 { > + cpu = <&cpu3>; > + }; Having separation lines between the cores here would be nice. > + }; > + > + cluster1 { > + core0 { > + cpu = <&cpu4>; > + }; > + core1 { > + cpu = <&cpu5>; > + }; > + core2 { > + cpu = <&cpu6>; > + }; > + core3 { > + cpu = <&cpu7>; > + }; > + }; > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu0: cpu@0 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x0>; > + }; > + > + cpu1: cpu@1 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x1>; > + }; > + > + cpu2: cpu@2 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x2>; > + }; > + > + cpu3: cpu@3 { > + compatible = "arm,cortex-a7"; > + device_type = "cpu"; > + reg = <0x3>; > + }; > + > + cpu4: cpu@100 { > + compatible = "arm,cortex-a15"; > + device_type = "cpu"; > + reg = <0x100>; > + }; > + > + cpu5: cpu@101 { > + compatible = "arm,cortex-a15"; > + device_type = "cpu"; > + reg = <0x101>; > + }; > + > + cpu6: cpu@102 { > + compatible = "arm,cortex-a15"; > + device_type = "cpu"; > + reg = <0x102>; > + }; > + > + cpu7: cpu@103 { > + compatible = "arm,cortex-a15"; > + device_type = "cpu"; > + reg = <0x103>; > + }; > + }; > + > + memory { > + reg = <0x20000000 0x40000000>; Usually, what we put there was the maximum amount of RAM that can be handled by the SoC. I think that it can go above 1GB It looks fine otherwise, thanks! Maxime
On Wed, Sep 24, 2014 at 2:37 PM, Maxime Ripard <maxime.ripard@free-electrons.com> wrote: > Hi, > > Thanks, a lot for your patches :) > > On Sun, Sep 21, 2014 at 10:58:10PM +0800, Chen-Yu Tsai wrote: >> The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and >> 4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core >> PowerVR G6230 GPU. >> >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> arch/arm/boot/dts/sun9i-a80.dtsi | 280 +++++++++++++++++++++++++++++++++++++++ >> 1 file changed, 280 insertions(+) >> create mode 100644 arch/arm/boot/dts/sun9i-a80.dtsi >> >> diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi >> new file mode 100644 >> index 0000000..f23ea59 >> --- /dev/null >> +++ b/arch/arm/boot/dts/sun9i-a80.dtsi >> @@ -0,0 +1,280 @@ >> +/* >> + * Copyright 2014 Chen-Yu Tsai >> + * >> + * Chen-Yu Tsai <wens@csie.org> >> + * >> + * This file is dual-licensed: you can use it either under the terms >> + * of the GPL or the X11 license, at your option. Note that this dual >> + * licensing only applies to this file, and not this project as a >> + * whole. >> + * >> + * a) This library is free software; you can redistribute it and/or >> + * modify it under the terms of the GNU General Public License as >> + * published by the Free Software Foundation; either version 2 of the >> + * License, or (at your option) any later version. >> + * >> + * This library is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + * >> + * You should have received a copy of the GNU General Public >> + * License along with this library; if not, write to the Free >> + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, >> + * MA 02110-1301 USA >> + * >> + * Or, alternatively, >> + * >> + * b) Permission is hereby granted, free of charge, to any person >> + * obtaining a copy of this software and associated documentation >> + * files (the "Software"), to deal in the Software without >> + * restriction, including without limitation the rights to use, >> + * copy, modify, merge, publish, distribute, sublicense, and/or >> + * sell copies of the Software, and to permit persons to whom the >> + * Software is furnished to do so, subject to the following >> + * conditions: >> + * >> + * The above copyright notice and this permission notice shall be >> + * included in all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, >> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES >> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND >> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT >> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, >> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING >> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR >> + * OTHER DEALINGS IN THE SOFTWARE. >> + */ >> + >> +/include/ "skeleton.dtsi" >> + >> +/ { >> + interrupt-parent = <&gic>; >> + >> + aliases { >> + serial0 = &uart0; >> + serial1 = &uart1; >> + serial2 = &uart2; >> + serial3 = &uart3; >> + serial4 = &uart4; >> + serial5 = &uart5; >> + serial6 = &r_uart; >> + }; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + core2 { >> + cpu = <&cpu2>; >> + }; >> + core3 { >> + cpu = <&cpu3>; >> + }; > > Having separation lines between the cores here would be nice. OK. >> + }; >> + >> + cluster1 { >> + core0 { >> + cpu = <&cpu4>; >> + }; >> + core1 { >> + cpu = <&cpu5>; >> + }; >> + core2 { >> + cpu = <&cpu6>; >> + }; >> + core3 { >> + cpu = <&cpu7>; >> + }; >> + }; >> + }; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0x0>; >> + }; >> + >> + cpu1: cpu@1 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0x1>; >> + }; >> + >> + cpu2: cpu@2 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0x2>; >> + }; >> + >> + cpu3: cpu@3 { >> + compatible = "arm,cortex-a7"; >> + device_type = "cpu"; >> + reg = <0x3>; >> + }; >> + >> + cpu4: cpu@100 { >> + compatible = "arm,cortex-a15"; >> + device_type = "cpu"; >> + reg = <0x100>; >> + }; >> + >> + cpu5: cpu@101 { >> + compatible = "arm,cortex-a15"; >> + device_type = "cpu"; >> + reg = <0x101>; >> + }; >> + >> + cpu6: cpu@102 { >> + compatible = "arm,cortex-a15"; >> + device_type = "cpu"; >> + reg = <0x102>; >> + }; >> + >> + cpu7: cpu@103 { >> + compatible = "arm,cortex-a15"; >> + device_type = "cpu"; >> + reg = <0x103>; >> + }; >> + }; >> + >> + memory { >> + reg = <0x20000000 0x40000000>; > > Usually, what we put there was the maximum amount of RAM that can be > handled by the SoC. I think that it can go above 1GB With LPAE, it can handle 8GB. But the DT won't take 64bit values. I'm not sure how to get it in. I'll look around for examples. > It looks fine otherwise, thanks! Thanks! ChenYu
Hi Chen-Yu, >>> + >>> + memory { >>> + reg = <0x20000000 0x40000000>; >> >> Usually, what we put there was the maximum amount of RAM that can be >> handled by the SoC. I think that it can go above 1GB > > With LPAE, it can handle 8GB. But the DT won't take 64bit values. > I'm not sure how to get it in. I'll look around for examples. You can have a look on what we did for Armada XP: arch/arm/boot/dts/armada-370-xp.dtsi arch/arm/boot/dts/armada-xp.dtsi arch/arm/boot/dts/armada-xp-gp.dts I created a skeleton64.dtsi for this case Gregory
On Wed, Sep 24, 2014 at 3:18 PM, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote: > Hi Chen-Yu, > > >>>> + >>>> + memory { >>>> + reg = <0x20000000 0x40000000>; >>> >>> Usually, what we put there was the maximum amount of RAM that can be >>> handled by the SoC. I think that it can go above 1GB >> >> With LPAE, it can handle 8GB. But the DT won't take 64bit values. >> I'm not sure how to get it in. I'll look around for examples. > > You can have a look on what we did for Armada XP: > > arch/arm/boot/dts/armada-370-xp.dtsi > arch/arm/boot/dts/armada-xp.dtsi > arch/arm/boot/dts/armada-xp-gp.dts > > I created a skeleton64.dtsi for this case Thanks! I was wondering what that was for. ChenYu
On Wed, Sep 24, 2014 at 3:18 PM, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote: > Hi Chen-Yu, > > >>>> + >>>> + memory { >>>> + reg = <0x20000000 0x40000000>; >>> >>> Usually, what we put there was the maximum amount of RAM that can be >>> handled by the SoC. I think that it can go above 1GB >> >> With LPAE, it can handle 8GB. But the DT won't take 64bit values. >> I'm not sure how to get it in. I'll look around for examples. > > You can have a look on what we did for Armada XP: > > arch/arm/boot/dts/armada-370-xp.dtsi > arch/arm/boot/dts/armada-xp.dtsi > arch/arm/boot/dts/armada-xp-gp.dts > > I created a skeleton64.dtsi for this case Thanks for the tip. Before I send v2, I do have a question. I'm using ranges = <0 0 0 0x20000000>; in the clocks and soc node to avoid having to use 64bit values for all addresses and sizes. Would this be undesirable, even bad practice maybe? http://linux-sunxi.org/A80/Memory_map is a document I pieced together from Allwinner's SDK header files. AFAIK only the memory goes above the 4GB limit. All peripherals are under 512 MB, 256MB even. Thanks ChenYu
Hi Chen-Yu, > > Thanks for the tip. Before I send v2, I do have a question. I'm using > > ranges = <0 0 0 0x20000000>; > > in the clocks and soc node to avoid having to use 64bit values for all > addresses and sizes. Would this be undesirable, even bad practice maybe? We did something like that for all the internal registers too as they are all under 4GB. In our case the use of a range really makes sens because the hardware addresses were configurable. You don't have such requirement so I can't say if it is a bad practice. From my point of view it seems sensible but I am not an DT expert. Grégory
diff --git a/arch/arm/boot/dts/sun9i-a80.dtsi b/arch/arm/boot/dts/sun9i-a80.dtsi new file mode 100644 index 0000000..f23ea59 --- /dev/null +++ b/arch/arm/boot/dts/sun9i-a80.dtsi @@ -0,0 +1,280 @@ +/* + * Copyright 2014 Chen-Yu Tsai + * + * Chen-Yu Tsai <wens@csie.org> + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public + * License along with this library; if not, write to the Free + * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&gic>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &r_uart; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0x3>; + }; + + cpu4: cpu@100 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x100>; + }; + + cpu5: cpu@101 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x101>; + }; + + cpu6: cpu@102 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x102>; + }; + + cpu7: cpu@103 { + compatible = "arm,cortex-a15"; + device_type = "cpu"; + reg = <0x103>; + }; + }; + + memory { + reg = <0x20000000 0x40000000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + osc24M: osc24M_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "osc24M"; + }; + + osc32k: osc32k_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + clock-output-names = "osc32k"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gic: interrupt-controller@01c41000 { + compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; + reg = <0x01c41000 0x1000>, + <0x01c42000 0x1000>, + <0x01c44000 0x2000>, + <0x01c46000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <1 9 0xf04>; + }; + + timer@06000c00 { + compatible = "allwinner,sun4i-a10-timer"; + reg = <0x06000c00 0xa0>; + interrupts = <0 18 4>, + <0 19 4>, + <0 20 4>, + <0 21 4>, + <0 22 4>, + <0 23 4>; + + clocks = <&osc24M>; + }; + + uart0: serial@07000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000000 0x400>; + interrupts = <0 0 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart1: serial@07000400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000400 0x400>; + interrupts = <0 1 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart2: serial@07000800 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000800 0x400>; + interrupts = <0 2 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart3: serial@07000c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x07000c00 0x400>; + interrupts = <0 3 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart4: serial@07001000 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001000 0x400>; + interrupts = <0 4 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + uart5: serial@07001400 { + compatible = "snps,dw-apb-uart"; + reg = <0x07001400 0x400>; + interrupts = <0 5 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + + r_wdt: watchdog@08001000 { + compatible = "allwinner,sun6i-a31-wdt"; + reg = <0x08001000 0x20>; + interrupts = <0 36 4>; + }; + + r_uart: serial@08002800 { + compatible = "snps,dw-apb-uart"; + reg = <0x08002800 0x400>; + interrupts = <0 38 4>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&osc24M>; + status = "disabled"; + }; + }; +};
The Allwinner A80 is a new multi-purpose SoC with 4 Cortex-A7 and 4 Cortex-A15 cores in a big.LITTLE architecture, and a 64-core PowerVR G6230 GPU. Signed-off-by: Chen-Yu Tsai <wens@csie.org> --- arch/arm/boot/dts/sun9i-a80.dtsi | 280 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 280 insertions(+) create mode 100644 arch/arm/boot/dts/sun9i-a80.dtsi