[v4,RFC] i2c: rk3x: handle dynamic clock rate changes correctly
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Message ID 38150529.7Nm2HqTn1y@typ
State New, archived
Headers show

Commit Message

Max Schwarz Sept. 22, 2014, 9:36 p.m. UTC
The i2c input clock can change dynamically, e.g. on the RK3066 where
pclk_i2c0 and pclk_i2c1 are connected to the armclk, which changes
rate on cpu frequency scaling.

Until now, we incorrectly called clk_get_rate() while holding the
i2c->lock in rk3x_i2c_xfer() to adapt to clock rate changes.
Thanks to Huang Tao for reporting this issue.

Do it properly now using the clk notifier framework. The callback
logic was taken from i2c-cadence.c.

Signed-off-by: Max Schwarz <max.schwarz@online.de>
Tested-by: Max Schwarz <max.schwarz@online.de> on RK3188
(dynamic rate changes are untested!)
---

This is based on Wolframs' i2c/for-current branch, since that
includes the recent divisor fix by Addy Ke (b4a7bd7a38).

Changes since v3:
 - drop leftover write-only clk_freq variable (sugg. by Doug Anderson)

Changes since v2:
 - allow rate changes which result in lower than
   desired SCL frequencies (sugg. by Doug Anderson)
 - simplified divider range checks (Doug Anderson)
 - removed duplicate clk_enable()/disable() (Doug Anderson)
 - added missing unregister in rk3x_i2c_remove() (Doug Anderson)

Changes since v1:
 - make sure the i2c input clock is active during prescaler
   register write by explicitly enabling/disabling it in
   rk3x_i2c_set_scl_frequency(). Bug found by Addy Ke.

It would still be awesome if someone with an RK3066 could test this.
Heiko suggested using a script by Doug for stress-testing frequency
changes:

cd /sys/devices/system/cpu/cpu0/cpufreq
echo userspace > scaling_governor
unset FREQS
read -a FREQS < scaling_available_frequencies
RANDOM=$$$(date +%s)
while true; do
  FREQ=${FREQS[$RANDOM % ${#FREQS[@]} ]}
  echo Now ${FREQ}
  echo ${FREQ} > scaling_setspeed
done

If you run some I2C transactions at the same time (e.g. using
i2cget) that would be enough to confirm that everything still
works.

Cheers,
  Max

 drivers/i2c/busses/i2c-rk3x.c | 128 +++++++++++++++++++++++++++++++++++++++---
 1 file changed, 120 insertions(+), 8 deletions(-)

Comments

Doug Anderson Sept. 22, 2014, 11:20 p.m. UTC | #1
Max,

On Mon, Sep 22, 2014 at 2:36 PM, Max Schwarz <max.schwarz@online.de> wrote:
> +       /*
> +        * We might be called from rk3x_i2c_probe or from the clk rate change
> +        * notifier. In that case, the i2c clk is not running. So enable it
> +        * explicitly here during the register write.

I still would have changed this comment to at least do "s/In that
case/in both cases"
...but I don't really care that much about this one, so:

Reviewed-by: Doug Anderson <dianders@chromium.org>

I've tested that this patch doesn't break my rk3288 board (though just
like you, I can't test the dynamic rate changes), so:

Tested-by: Doug Anderson <dianders@chromium.org>

Patch
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diff --git a/drivers/i2c/busses/i2c-rk3x.c b/drivers/i2c/busses/i2c-rk3x.c
index 93cfc83..7f5e440 100644
--- a/drivers/i2c/busses/i2c-rk3x.c
+++ b/drivers/i2c/busses/i2c-rk3x.c
@@ -97,6 +97,7 @@  struct rk3x_i2c {
 	/* Hardware resources */
 	void __iomem *regs;
 	struct clk *clk;
+	struct notifier_block clk_rate_nb;
 
 	/* Settings */
 	unsigned int scl_frequency;
@@ -428,18 +429,119 @@  out:
 	return IRQ_HANDLED;
 }
 
-static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
+/**
+ * Calculate divider value for desired SCL frequency
+ *
+ * @clk_rate: I2C input clock rate
+ * @scl_rate: Desired SCL rate
+ * @div:      Divider output
+ *
+ * Return:    0 on success, -EINVAL on unreachable SCL rate. In that case
+ *            a best-effort divider value is returned in div.
+ **/
+static int rk3x_i2c_calc_div(unsigned long clk_rate, unsigned long scl_rate,
+			     unsigned int *div)
 {
-	unsigned long i2c_rate = clk_get_rate(i2c->clk);
-	unsigned int div;
+	unsigned long div_tmp;
 
 	/* set DIV = DIVH = DIVL
 	 * SCL rate = (clk rate) / (8 * (DIVH + 1 + DIVL + 1))
 	 *          = (clk rate) / (16 * (DIV + 1))
 	 */
-	div = DIV_ROUND_UP(i2c_rate, scl_rate * 16) - 1;
+	div_tmp = DIV_ROUND_UP(clk_rate, scl_rate * 16) - 1;
 
+	if (div_tmp > 0xFFFF) {
+		/* The input clock is too fast. Reject this rate change. */
+		*div = 0xFFFF;
+		return -EINVAL;
+	}
+
+	*div = div_tmp;
+
+	return 0;
+}
+
+/**
+ * Setup divider register for desired SCL frequency
+ *
+ * @scl_rate: Desired SCL Rate
+ **/
+static void rk3x_i2c_set_scl_rate(struct rk3x_i2c *i2c, unsigned long scl_rate)
+{
+	unsigned long i2c_rate = clk_get_rate(i2c->clk);
+	unsigned int div;
+	int ret;
+
+	ret = rk3x_i2c_calc_div(i2c_rate, scl_rate, &div);
+
+	WARN_ONCE(ret != 0, "Could not reach desired SCL freq %lu", scl_rate);
+
+	/*
+	 * We might be called from rk3x_i2c_probe or from the clk rate change
+	 * notifier. In that case, the i2c clk is not running. So enable it
+	 * explicitly here during the register write.
+	 *
+	 * Writing the register with halted clock crashes the system at least on
+	 * RK3288.
+	 */
+
+	clk_enable(i2c->clk);
 	i2c_writel(i2c, (div << 16) | (div & 0xffff), REG_CLKDIV);
+	clk_disable(i2c->clk);
+}
+
+/**
+ * rk3x_i2c_clk_notifier_cb - Clock rate change callback
+ * @nb:		Pointer to notifier block
+ * @event:	Notification reason
+ * @data:	Pointer to notification data object
+ *
+ * The callback checks whether a valid bus frequency can be generated after the
+ * change. If so, the change is acknowledged, otherwise the change is aborted.
+ * New dividers are written to the HW in the pre- or post change notification
+ * depending on the scaling direction.
+ *
+ * Code adapted from i2c-cadence.c.
+ *
+ * Return:	NOTIFY_STOP if the rate change should be aborted, NOTIFY_OK
+ *		to acknowedge the change, NOTIFY_DONE if the notification is
+ *		considered irrelevant.
+ */
+static int rk3x_i2c_clk_notifier_cb(struct notifier_block *nb, unsigned long
+				    event, void *data)
+{
+	struct clk_notifier_data *ndata = data;
+	struct rk3x_i2c *i2c = container_of(nb, struct rk3x_i2c, clk_rate_nb);
+
+	switch (event) {
+	case PRE_RATE_CHANGE:
+	{
+		unsigned int div;
+
+		if (rk3x_i2c_calc_div(ndata->new_rate, i2c->scl_frequency,
+				      &div) != 0) {
+			return NOTIFY_STOP;
+		}
+
+		/* scale up */
+		if (ndata->new_rate > ndata->old_rate)
+			rk3x_i2c_set_scl_rate(i2c, ndata->new_rate);
+
+		return NOTIFY_OK;
+	}
+	case POST_RATE_CHANGE:
+		/* scale down */
+		if (ndata->new_rate < ndata->old_rate)
+			rk3x_i2c_set_scl_rate(i2c, ndata->new_rate);
+		return NOTIFY_OK;
+	case ABORT_RATE_CHANGE:
+		/* scale up */
+		if (ndata->new_rate > ndata->old_rate)
+			rk3x_i2c_set_scl_rate(i2c, ndata->old_rate);
+		return NOTIFY_OK;
+	default:
+		return NOTIFY_DONE;
+	}
 }
 
 /**
@@ -536,9 +638,6 @@  static int rk3x_i2c_xfer(struct i2c_adapter *adap,
 
 	clk_enable(i2c->clk);
 
-	/* The clock rate might have changed, so setup the divider again */
-	rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
-
 	i2c->is_last_msg = false;
 
 	/*
@@ -724,16 +823,27 @@  static int rk3x_i2c_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	i2c->clk_rate_nb.notifier_call = rk3x_i2c_clk_notifier_cb;
+	ret = clk_notifier_register(i2c->clk, &i2c->clk_rate_nb);
+	if (ret != 0) {
+		dev_err(&pdev->dev, "Unable to register clock notifier\n");
+		goto err_clk;
+	}
+
+	rk3x_i2c_set_scl_rate(i2c, i2c->scl_frequency);
+
 	ret = i2c_add_adapter(&i2c->adap);
 	if (ret < 0) {
 		dev_err(&pdev->dev, "Could not register adapter\n");
-		goto err_clk;
+		goto err_clk_notifier;
 	}
 
 	dev_info(&pdev->dev, "Initialized RK3xxx I2C bus at %p\n", i2c->regs);
 
 	return 0;
 
+err_clk_notifier:
+	clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
 err_clk:
 	clk_unprepare(i2c->clk);
 	return ret;
@@ -744,6 +854,8 @@  static int rk3x_i2c_remove(struct platform_device *pdev)
 	struct rk3x_i2c *i2c = platform_get_drvdata(pdev);
 
 	i2c_del_adapter(&i2c->adap);
+
+	clk_notifier_unregister(i2c->clk, &i2c->clk_rate_nb);
 	clk_unprepare(i2c->clk);
 
 	return 0;