diff mbox

[v2,1/2] drm/radeon: Try placing NO_CPU_ACCESS BOs outside of CPU accessible VRAM

Message ID 1412911716-1580-1-git-send-email-michel@daenzer.net (mailing list archive)
State New, archived
Headers show

Commit Message

Michel Dänzer Oct. 10, 2014, 3:28 a.m. UTC 
From: Michel Dänzer <michel.daenzer@amd.com>

This avoids them getting in the way of BOs which might be accessed by
the CPU. They can still go to the CPU accessible part of VRAM though if
there's no space outside of it.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
---

v2: Bump size of struct radeon_bo placements array.

 drivers/gpu/drm/radeon/radeon.h        |  2 +-
 drivers/gpu/drm/radeon/radeon_object.c | 42 ++++++++++++++++++++++++++++------
 2 files changed, 36 insertions(+), 8 deletions(-)

Comments

Alex Deucher Oct. 13, 2014, 6:25 p.m. UTC | #1 
On Thu, Oct 9, 2014 at 11:28 PM, Michel Dänzer <michel@daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer@amd.com>
>
> This avoids them getting in the way of BOs which might be accessed by
> the CPU. They can still go to the CPU accessible part of VRAM though if
> there's no space outside of it.
>
> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>

Applied this series to my 3.19 tree.

Alex

> ---
>
> v2: Bump size of struct radeon_bo placements array.
>
>  drivers/gpu/drm/radeon/radeon.h        |  2 +-
>  drivers/gpu/drm/radeon/radeon_object.c | 42 ++++++++++++++++++++++++++++------
>  2 files changed, 36 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index f7c4b22..11e56ff 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -474,7 +474,7 @@ struct radeon_bo {
>         struct list_head                list;
>         /* Protected by tbo.reserved */
>         u32                             initial_domain;
> -       struct ttm_place                placements[3];
> +       struct ttm_place                placements[4];
>         struct ttm_placement            placement;
>         struct ttm_buffer_object        tbo;
>         struct ttm_bo_kmap_obj          kmap;
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
> index 99a960a..7f3b1e1 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -99,22 +99,39 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
>
>         rbo->placement.placement = rbo->placements;
>         rbo->placement.busy_placement = rbo->placements;
> -       if (domain & RADEON_GEM_DOMAIN_VRAM)
> +       if (domain & RADEON_GEM_DOMAIN_VRAM) {
> +               /* Try placing BOs which don't need CPU access outside of the
> +                * CPU accessible part of VRAM
> +                */
> +               if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
> +                   rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
> +                       rbo->placements[c].fpfn =
> +                               rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
> +                       rbo->placements[c++].flags = TTM_PL_FLAG_WC |
> +                                                    TTM_PL_FLAG_UNCACHED |
> +                                                    TTM_PL_FLAG_VRAM;
> +               }
> +
> +               rbo->placements[c].fpfn = 0;
>                 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
>                                              TTM_PL_FLAG_UNCACHED |
>                                              TTM_PL_FLAG_VRAM;
> +       }
>
>         if (domain & RADEON_GEM_DOMAIN_GTT) {
>                 if (rbo->flags & RADEON_GEM_GTT_UC) {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
>                                 TTM_PL_FLAG_TT;
>
>                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
>                            (rbo->rdev->flags & RADEON_IS_AGP)) {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
>                                 TTM_PL_FLAG_UNCACHED |
>                                 TTM_PL_FLAG_TT;
>                 } else {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
>                                                      TTM_PL_FLAG_TT;
>                 }
> @@ -122,30 +139,35 @@ void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
>
>         if (domain & RADEON_GEM_DOMAIN_CPU) {
>                 if (rbo->flags & RADEON_GEM_GTT_UC) {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
>                                 TTM_PL_FLAG_SYSTEM;
>
>                 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
>                     rbo->rdev->flags & RADEON_IS_AGP) {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_WC |
>                                 TTM_PL_FLAG_UNCACHED |
>                                 TTM_PL_FLAG_SYSTEM;
>                 } else {
> +                       rbo->placements[c].fpfn = 0;
>                         rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
>                                                      TTM_PL_FLAG_SYSTEM;
>                 }
>         }
> -       if (!c)
> +       if (!c) {
> +               rbo->placements[c].fpfn = 0;
>                 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
>                                              TTM_PL_FLAG_SYSTEM;
> +       }
>
>         rbo->placement.num_placement = c;
>         rbo->placement.num_busy_placement = c;
>
>         for (i = 0; i < c; ++i) {
> -               rbo->placements[i].fpfn = 0;
>                 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
> -                   (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
> +                   (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
> +                   !rbo->placements[i].fpfn)
>                         rbo->placements[i].lpfn =
>                                 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>                 else
> @@ -743,8 +765,8 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>  {
>         struct radeon_device *rdev;
>         struct radeon_bo *rbo;
> -       unsigned long offset, size;
> -       int r;
> +       unsigned long offset, size, lpfn;
> +       int i, r;
>
>         if (!radeon_ttm_bo_is_radeon_bo(bo))
>                 return 0;
> @@ -761,7 +783,13 @@ int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
>
>         /* hurrah the memory is not visible ! */
>         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
> -       rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
> +       lpfn =  rdev->mc.visible_vram_size >> PAGE_SHIFT;
> +       for (i = 0; i < rbo->placement.num_placement; i++) {
> +               /* Force into visible VRAM */
> +               if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
> +                   (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
> +                       rbo->placements[i].lpfn = lpfn;
> +       }
>         r = ttm_bo_validate(bo, &rbo->placement, false, false);
>         if (unlikely(r == -ENOMEM)) {
>                 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
> --
> 2.1.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index f7c4b22..11e56ff 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -474,7 +474,7 @@  struct radeon_bo {
 	struct list_head		list;
 	/* Protected by tbo.reserved */
 	u32				initial_domain;
-	struct ttm_place		placements[3];
+	struct ttm_place		placements[4];
 	struct ttm_placement		placement;
 	struct ttm_buffer_object	tbo;
 	struct ttm_bo_kmap_obj		kmap;
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 99a960a..7f3b1e1 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -99,22 +99,39 @@  void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 
 	rbo->placement.placement = rbo->placements;
 	rbo->placement.busy_placement = rbo->placements;
-	if (domain & RADEON_GEM_DOMAIN_VRAM)
+	if (domain & RADEON_GEM_DOMAIN_VRAM) {
+		/* Try placing BOs which don't need CPU access outside of the
+		 * CPU accessible part of VRAM
+		 */
+		if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
+		    rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
+			rbo->placements[c].fpfn =
+				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
+			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
+						     TTM_PL_FLAG_UNCACHED |
+						     TTM_PL_FLAG_VRAM;
+		}
+
+		rbo->placements[c].fpfn = 0;
 		rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 					     TTM_PL_FLAG_UNCACHED |
 					     TTM_PL_FLAG_VRAM;
+	}
 
 	if (domain & RADEON_GEM_DOMAIN_GTT) {
 		if (rbo->flags & RADEON_GEM_GTT_UC) {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_TT;
 
 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 			   (rbo->rdev->flags & RADEON_IS_AGP)) {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 				TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_TT;
 		} else {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 						     TTM_PL_FLAG_TT;
 		}
@@ -122,30 +139,35 @@  void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
 
 	if (domain & RADEON_GEM_DOMAIN_CPU) {
 		if (rbo->flags & RADEON_GEM_GTT_UC) {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_SYSTEM;
 
 		} else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
 		    rbo->rdev->flags & RADEON_IS_AGP) {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_WC |
 				TTM_PL_FLAG_UNCACHED |
 				TTM_PL_FLAG_SYSTEM;
 		} else {
+			rbo->placements[c].fpfn = 0;
 			rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
 						     TTM_PL_FLAG_SYSTEM;
 		}
 	}
-	if (!c)
+	if (!c) {
+		rbo->placements[c].fpfn = 0;
 		rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
 					     TTM_PL_FLAG_SYSTEM;
+	}
 
 	rbo->placement.num_placement = c;
 	rbo->placement.num_busy_placement = c;
 
 	for (i = 0; i < c; ++i) {
-		rbo->placements[i].fpfn = 0;
 		if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
-		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM))
+		    (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
+		    !rbo->placements[i].fpfn)
 			rbo->placements[i].lpfn =
 				rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 		else
@@ -743,8 +765,8 @@  int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 {
 	struct radeon_device *rdev;
 	struct radeon_bo *rbo;
-	unsigned long offset, size;
-	int r;
+	unsigned long offset, size, lpfn;
+	int i, r;
 
 	if (!radeon_ttm_bo_is_radeon_bo(bo))
 		return 0;
@@ -761,7 +783,13 @@  int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 
 	/* hurrah the memory is not visible ! */
 	radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
-	rbo->placements[0].lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
+	lpfn =	rdev->mc.visible_vram_size >> PAGE_SHIFT;
+	for (i = 0; i < rbo->placement.num_placement; i++) {
+		/* Force into visible VRAM */
+		if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
+		    (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
+			rbo->placements[i].lpfn = lpfn;
+	}
 	r = ttm_bo_validate(bo, &rbo->placement, false, false);
 	if (unlikely(r == -ENOMEM)) {
 		radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);