| Message ID | 1415382301-31444-1-git-send-email-daniele.ceraolospurio@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Nov 07, 2014 at 05:45:01PM +0000, daniele.ceraolospurio@intel.com wrote: > +/** > + * DOC: execlist_submit_context tracepoint > + * > + * These tracepoint are used to track the contexts that are submitted to the > + * ring. An mm switch is automatically performed by the GPU during the context > + * switch. Given the fact that the mm switch is an important point in the > + * lifetime of a vm, the vm assigned to the context is also printed by the > + * tracepoint when full ppgtt is enabled. > + */ > +TRACE_EVENT(execlists_submit_context, > + TP_PROTO(struct intel_engine_cs *ring, u32 to_num, struct intel_context *to), > + > + TP_ARGS(ring, to_num, to), > + > + TP_STRUCT__entry( > + __field(u32, ring) > + __field(u32, to_num) > + __field(struct intel_context *, to) > + __field(struct i915_address_space *, vm) > + __field(u32, dev) > + ), > + > + TP_fast_assign( > + __entry->ring = ring->id; > + __entry->to_num = to_num; > + __entry->to = to; > + __entry->vm = to->ppgtt ? &to->ppgtt->base : NULL; > + __entry->dev = ring->dev->primary->index; > + ), > + > + TP_printk("dev=%u, ring=%u, ctx%d=%p, ctx_vm=%p", > + __entry->dev, __entry->ring, > + __entry->to_num, __entry->to, __entry->vm) > +); > + > #endif /* _I915_TRACE_H_ */ > > /* This part must be outside protection */ > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 6025ac7..e72759d 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -135,6 +135,7 @@ > #include <drm/drmP.h> > #include <drm/i915_drm.h> > #include "i915_drv.h" > +#include "i915_trace.h" > > #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) > #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) > @@ -367,6 +368,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, > BUG_ON(!ctx_obj0); > WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); > > + trace_execlists_submit_context(ring, 0, to0); > execlists_ctx_write_tail(ctx_obj0, tail0); This is very tenuous. This is not part of the context lifetime but of the request. -Chris
On 11/10/2014 11:40 AM, Ceraolo Spurio, Daniele wrote: > On 11/8/2014 8:44 AM, Chris Wilson wrote: >> On Fri, Nov 07, 2014 at 05:45:01PM +0000, >> daniele.ceraolospurio@intel.com wrote: >>> +/** >>> + * DOC: execlist_submit_context tracepoint >>> + * >>> + * These tracepoint are used to track the contexts that are >>> submitted to the >>> + * ring. An mm switch is automatically performed by the GPU during >>> the context >>> + * switch. Given the fact that the mm switch is an important point >>> in the >>> + * lifetime of a vm, the vm assigned to the context is also printed >>> by the >>> + * tracepoint when full ppgtt is enabled. >>> + */ >>> +TRACE_EVENT(execlists_submit_context, >>> + TP_PROTO(struct intel_engine_cs *ring, u32 to_num, struct >>> intel_context *to), >>> + >>> + TP_ARGS(ring, to_num, to), >>> + >>> + TP_STRUCT__entry( >>> + __field(u32, ring) >>> + __field(u32, to_num) >>> + __field(struct intel_context *, to) >>> + __field(struct i915_address_space *, vm) >>> + __field(u32, dev) >>> + ), >>> + >>> + TP_fast_assign( >>> + __entry->ring = ring->id; >>> + __entry->to_num = to_num; >>> + __entry->to = to; >>> + __entry->vm = to->ppgtt ? &to->ppgtt->base : NULL; >>> + __entry->dev = ring->dev->primary->index; >>> + ), >>> + >>> + TP_printk("dev=%u, ring=%u, ctx%d=%p, ctx_vm=%p", >>> + __entry->dev, __entry->ring, >>> + __entry->to_num, __entry->to, __entry->vm) >>> +); >>> + >>> #endif /* _I915_TRACE_H_ */ >>> >>> /* This part must be outside protection */ >>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c >>> b/drivers/gpu/drm/i915/intel_lrc.c >>> index 6025ac7..e72759d 100644 >>> --- a/drivers/gpu/drm/i915/intel_lrc.c >>> +++ b/drivers/gpu/drm/i915/intel_lrc.c >>> @@ -135,6 +135,7 @@ >>> #include <drm/drmP.h> >>> #include <drm/i915_drm.h> >>> #include "i915_drv.h" >>> +#include "i915_trace.h" >>> >>> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) >>> #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) >>> @@ -367,6 +368,7 @@ static void execlists_submit_contexts(struct >>> intel_engine_cs *ring, >>> BUG_ON(!ctx_obj0); >>> WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); >>> >>> + trace_execlists_submit_context(ring, 0, to0); >>> execlists_ctx_write_tail(ctx_obj0, tail0); >> >> This is very tenuous. This is not part of the context lifetime but of >> the request. >> -Chris >> > > The aim wasn't to track the context or the request but to track the > switch_mm. considering that in execlist mode that is automatically done > by the GPU when the ctx is moved on the ring, this looked like a good > place to put the trace. What were you exactly concerned about? > > Thanks, > Daniele > + intel-gfx
On 11/10/2014 11:54 AM, Chris Wilson wrote: > On Mon, Nov 10, 2014 at 11:40:40AM +0000, Ceraolo Spurio, Daniele wrote: >> On 11/8/2014 8:44 AM, Chris Wilson wrote: >>> On Fri, Nov 07, 2014 at 05:45:01PM +0000, daniele.ceraolospurio@intel.com wrote: >>>> +/** >>>> + * DOC: execlist_submit_context tracepoint >>>> + * >>>> + * These tracepoint are used to track the contexts that are submitted to the >>>> + * ring. An mm switch is automatically performed by the GPU during the context >>>> + * switch. Given the fact that the mm switch is an important point in the >>>> + * lifetime of a vm, the vm assigned to the context is also printed by the >>>> + * tracepoint when full ppgtt is enabled. >>>> + */ >>>> +TRACE_EVENT(execlists_submit_context, >>>> + TP_PROTO(struct intel_engine_cs *ring, u32 to_num, struct intel_context *to), >>>> + >>>> + TP_ARGS(ring, to_num, to), >>>> + >>>> + TP_STRUCT__entry( >>>> + __field(u32, ring) >>>> + __field(u32, to_num) >>>> + __field(struct intel_context *, to) >>>> + __field(struct i915_address_space *, vm) >>>> + __field(u32, dev) >>>> + ), >>>> + >>>> + TP_fast_assign( >>>> + __entry->ring = ring->id; >>>> + __entry->to_num = to_num; >>>> + __entry->to = to; >>>> + __entry->vm = to->ppgtt ? &to->ppgtt->base : NULL; >>>> + __entry->dev = ring->dev->primary->index; >>>> + ), >>>> + >>>> + TP_printk("dev=%u, ring=%u, ctx%d=%p, ctx_vm=%p", >>>> + __entry->dev, __entry->ring, >>>> + __entry->to_num, __entry->to, __entry->vm) >>>> +); >>>> + >>>> #endif /* _I915_TRACE_H_ */ >>>> >>>> /* This part must be outside protection */ >>>> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c >>>> index 6025ac7..e72759d 100644 >>>> --- a/drivers/gpu/drm/i915/intel_lrc.c >>>> +++ b/drivers/gpu/drm/i915/intel_lrc.c >>>> @@ -135,6 +135,7 @@ >>>> #include <drm/drmP.h> >>>> #include <drm/i915_drm.h> >>>> #include "i915_drv.h" >>>> +#include "i915_trace.h" >>>> >>>> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) >>>> #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) >>>> @@ -367,6 +368,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, >>>> BUG_ON(!ctx_obj0); >>>> WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); >>>> >>>> + trace_execlists_submit_context(ring, 0, to0); >>>> execlists_ctx_write_tail(ctx_obj0, tail0); >>> >>> This is very tenuous. This is not part of the context lifetime but of >>> the request. >>> -Chris >>> >> >> The aim wasn't to track the context or the request but to track the >> switch_mm. considering that in execlist mode that is automatically >> done by the GPU when the ctx is moved on the ring, this looked like >> a good place to put the trace. What were you exactly concerned >> about? > > I have a different pattern for the lifetimes in my head. In terms of > usage tracking, when the context is submitted is to hardware is more or > less irrelevant to the lifetime per se - it is interesting, but only > in the context of tracking the execlists/scheduler. > > For the context, the important point is when a new request (e.g. > execbuffer) is created from that context, which will then keep that > context alive until the request is complete. That's my > switch_mm/switch_context equivalent. (I think I have refined my stance a > lot since working with the contexts and requests). > > The other perspective, is that I want the context tracepoints to be > actions on the contexts themselves, rather than actions on the hardware > which deserve to be in a different domain. (Obviously in the overlap, > there will be some arguing as to which domain it best fits in.) > I am trying to keep the tracepoints somewhat logically organised. :| > -Chris > + intel-gfx, which I've inadvertently removed in my previous reply. I now understand what you meant and I can see your point. However, since I'm still getting familiar with the handling of contexts in the driver (execlists etc), I'll have to dig a bit more to find the right places for tracepoints. Would it be ok for you if I were to drop the submit_context trace for now and just go on with the others? I'll get back to this part when I feel more comfortable with my understanding of the code. Thanks, Daniele
On Mon, Nov 10, 2014 at 12:28:11PM +0000, Ceraolo Spurio, Daniele wrote: > On 11/10/2014 11:54 AM, Chris Wilson wrote: > >On Mon, Nov 10, 2014 at 11:40:40AM +0000, Ceraolo Spurio, Daniele wrote: > >>On 11/8/2014 8:44 AM, Chris Wilson wrote: > >>>On Fri, Nov 07, 2014 at 05:45:01PM +0000, daniele.ceraolospurio@intel.com wrote: > >>>>+/** > >>>>+ * DOC: execlist_submit_context tracepoint > >>>>+ * > >>>>+ * These tracepoint are used to track the contexts that are submitted to the > >>>>+ * ring. An mm switch is automatically performed by the GPU during the context > >>>>+ * switch. Given the fact that the mm switch is an important point in the > >>>>+ * lifetime of a vm, the vm assigned to the context is also printed by the > >>>>+ * tracepoint when full ppgtt is enabled. > >>>>+ */ > >>>>+TRACE_EVENT(execlists_submit_context, > >>>>+ TP_PROTO(struct intel_engine_cs *ring, u32 to_num, struct intel_context *to), > >>>>+ > >>>>+ TP_ARGS(ring, to_num, to), > >>>>+ > >>>>+ TP_STRUCT__entry( > >>>>+ __field(u32, ring) > >>>>+ __field(u32, to_num) > >>>>+ __field(struct intel_context *, to) > >>>>+ __field(struct i915_address_space *, vm) > >>>>+ __field(u32, dev) > >>>>+ ), > >>>>+ > >>>>+ TP_fast_assign( > >>>>+ __entry->ring = ring->id; > >>>>+ __entry->to_num = to_num; > >>>>+ __entry->to = to; > >>>>+ __entry->vm = to->ppgtt ? &to->ppgtt->base : NULL; > >>>>+ __entry->dev = ring->dev->primary->index; > >>>>+ ), > >>>>+ > >>>>+ TP_printk("dev=%u, ring=%u, ctx%d=%p, ctx_vm=%p", > >>>>+ __entry->dev, __entry->ring, > >>>>+ __entry->to_num, __entry->to, __entry->vm) > >>>>+); > >>>>+ > >>>> #endif /* _I915_TRACE_H_ */ > >>>> > >>>> /* This part must be outside protection */ > >>>>diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > >>>>index 6025ac7..e72759d 100644 > >>>>--- a/drivers/gpu/drm/i915/intel_lrc.c > >>>>+++ b/drivers/gpu/drm/i915/intel_lrc.c > >>>>@@ -135,6 +135,7 @@ > >>>> #include <drm/drmP.h> > >>>> #include <drm/i915_drm.h> > >>>> #include "i915_drv.h" > >>>>+#include "i915_trace.h" > >>>> > >>>> #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) > >>>> #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) > >>>>@@ -367,6 +368,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, > >>>> BUG_ON(!ctx_obj0); > >>>> WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); > >>>> > >>>>+ trace_execlists_submit_context(ring, 0, to0); > >>>> execlists_ctx_write_tail(ctx_obj0, tail0); > >>> > >>>This is very tenuous. This is not part of the context lifetime but of > >>>the request. > >>>-Chris > >>> > >> > >>The aim wasn't to track the context or the request but to track the > >>switch_mm. considering that in execlist mode that is automatically > >>done by the GPU when the ctx is moved on the ring, this looked like > >>a good place to put the trace. What were you exactly concerned > >>about? > > > >I have a different pattern for the lifetimes in my head. In terms of > >usage tracking, when the context is submitted is to hardware is more or > >less irrelevant to the lifetime per se - it is interesting, but only > >in the context of tracking the execlists/scheduler. > > > >For the context, the important point is when a new request (e.g. > >execbuffer) is created from that context, which will then keep that > >context alive until the request is complete. That's my > >switch_mm/switch_context equivalent. (I think I have refined my stance a > >lot since working with the contexts and requests). > > > >The other perspective, is that I want the context tracepoints to be > >actions on the contexts themselves, rather than actions on the hardware > >which deserve to be in a different domain. (Obviously in the overlap, > >there will be some arguing as to which domain it best fits in.) > >I am trying to keep the tracepoints somewhat logically organised. :| > >-Chris > > > > + intel-gfx, which I've inadvertently removed in my previous reply. > > I now understand what you meant and I can see your point. However, > since I'm still getting familiar with the handling of contexts in > the driver (execlists etc), I'll have to dig a bit more to find the > right places for tracepoints. Would it be ok for you if I were to > drop the submit_context trace for now and just go on with the > others? I'll get back to this part when I feel more comfortable with > my understanding of the code. Yes, all the others looked good to me. Please just drop the contentious tracepoint inside execlists, and slap on my Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (we will end up one in execlists, just probably as part of a different set of tracepoints ;) -Chris
diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl index 7277a7f..16e67eb 100644 --- a/Documentation/DocBook/drm.tmpl +++ b/Documentation/DocBook/drm.tmpl @@ -3994,6 +3994,31 @@ int num_ioctls;</synopsis> !Idrivers/gpu/drm/i915/intel_lrc.c </sect2> </sect1> + + <sect1> + <title> Tracing </title> + <para> + This sections covers all things related to the tracepoints implemented in + the i915 driver. + </para> + <sect2> + <title> i915_ppgtt_create and i915_ppgtt_release </title> +!Pdrivers/gpu/drm/i915/i915_trace.h i915_ppgtt_create and i915_ppgtt_release tracepoints + </sect2> + <sect2> + <title> i915_context_create and i915_context_free </title> +!Pdrivers/gpu/drm/i915/i915_trace.h i915_context_create and i915_context_free tracepoints + </sect2> + <sect2> + <title> switch_mm </title> +!Pdrivers/gpu/drm/i915/i915_trace.h switch_mm tracepoint + </sect2> + <sect2> + <title> execlist_submit_context </title> +!Pdrivers/gpu/drm/i915/i915_trace.h execlist_submit_context tracepoint + </sect2> + </sect1> + </chapter> !Cdrivers/gpu/drm/i915/i915_irq.c </part> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 7d32571..1fb0000 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -88,6 +88,7 @@ #include <drm/drmP.h> #include <drm/i915_drm.h> #include "i915_drv.h" +#include "i915_trace.h" /* This is a HW constraint. The value below is the largest known requirement * I've seen in a spec to date, and that was a workaround for a non-shipping @@ -137,6 +138,8 @@ void i915_gem_context_free(struct kref *ctx_ref) struct intel_context *ctx = container_of(ctx_ref, typeof(*ctx), ref); + trace_i915_context_free(ctx); + if (i915.enable_execlists) intel_lr_context_free(ctx); @@ -274,6 +277,8 @@ i915_gem_create_context(struct drm_device *dev, ctx->ppgtt = ppgtt; } + trace_i915_context_create(ctx); + return ctx; err_unpin: @@ -549,6 +554,7 @@ static int do_switch(struct intel_engine_cs *ring, from = ring->last_context; if (to->ppgtt) { + trace_switch_mm(ring, to); ret = to->ppgtt->switch_mm(to->ppgtt, ring); if (ret) goto unpin_out; diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c1cf332..7737e55 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -1174,6 +1174,8 @@ i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) ppgtt->file_priv = fpriv; + trace_i915_ppgtt_create(&ppgtt->base); + return ppgtt; } @@ -1182,6 +1184,8 @@ void i915_ppgtt_release(struct kref *kref) struct i915_hw_ppgtt *ppgtt = container_of(kref, struct i915_hw_ppgtt, ref); + trace_i915_ppgtt_release(&ppgtt->base); + /* vmas should already be unbound */ WARN_ON(!list_empty(&ppgtt->base.active_list)); WARN_ON(!list_empty(&ppgtt->base.inactive_list)); diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h index f5aa006..1d25018 100644 --- a/drivers/gpu/drm/i915/i915_trace.h +++ b/drivers/gpu/drm/i915/i915_trace.h @@ -587,6 +587,145 @@ TRACE_EVENT(intel_gpu_freq_change, TP_printk("new_freq=%u", __entry->freq) ); +/** + * DOC: i915_ppgtt_create and i915_ppgtt_release tracepoints + * + * With full ppgtt enabled each process using drm will allocate at least one + * translation table. With these traces it is possible to keep track of the + * allocation and of the lifetime of the tables; this can be used during + * testing/debug to verify that we are not leaking ppgtts. + * These traces identify the ppgtt through the vm pointer, which is also printed + * by the i915_vma_bind and i915_vma_unbind tracepoints. + */ +DECLARE_EVENT_CLASS(i915_ppgtt, + TP_PROTO(struct i915_address_space *vm), + TP_ARGS(vm), + + TP_STRUCT__entry( + __field(struct i915_address_space *, vm) + __field(u32, dev) + ), + + TP_fast_assign( + __entry->vm = vm; + __entry->dev = vm->dev->primary->index; + ), + + TP_printk("dev=%u, vm=%p", __entry->dev, __entry->vm) +) + +DEFINE_EVENT(i915_ppgtt, i915_ppgtt_create, + TP_PROTO(struct i915_address_space *vm), + TP_ARGS(vm) +); + +DEFINE_EVENT(i915_ppgtt, i915_ppgtt_release, + TP_PROTO(struct i915_address_space *vm), + TP_ARGS(vm) +); + +/** + * DOC: i915_context_create and i915_context_free tracepoints + * + * These tracepoints are used to track creation and deletion of contexts. + * If full ppgtt is enabled, they also print the address of the vm assigned to + * the context. + */ +DECLARE_EVENT_CLASS(i915_context, + TP_PROTO(struct intel_context *ctx), + TP_ARGS(ctx), + + TP_STRUCT__entry( + __field(u32, dev) + __field(struct intel_context *, ctx) + __field(struct i915_address_space *, vm) + ), + + TP_fast_assign( + __entry->ctx = ctx; + __entry->vm = ctx->ppgtt ? &ctx->ppgtt->base : NULL; + __entry->dev = ctx->file_priv->dev_priv->dev->primary->index; + ), + + TP_printk("dev=%u, ctx=%p, ctx_vm=%p", + __entry->dev, __entry->ctx, __entry->vm) +) + +DEFINE_EVENT(i915_context, i915_context_create, + TP_PROTO(struct intel_context *ctx), + TP_ARGS(ctx) +); + +DEFINE_EVENT(i915_context, i915_context_free, + TP_PROTO(struct intel_context *ctx), + TP_ARGS(ctx) +); + +/** + * DOC: switch_mm tracepoint + * + * This tracepoint allows tracking of the mm switch, which is an important point + * in the lifetime of the vm in the legacy submission path. This tracepoint is + * called only if full ppgtt is enabled. + */ +TRACE_EVENT(switch_mm, + TP_PROTO(struct intel_engine_cs *ring, struct intel_context *to), + + TP_ARGS(ring, to), + + TP_STRUCT__entry( + __field(u32, ring) + __field(struct intel_context *, to) + __field(struct i915_address_space *, vm) + __field(u32, dev) + ), + + TP_fast_assign( + __entry->ring = ring->id; + __entry->to = to; + __entry->vm = to->ppgtt? &to->ppgtt->base : NULL; + __entry->dev = ring->dev->primary->index; + ), + + TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p", + __entry->dev, __entry->ring, __entry->to, __entry->vm) +); + +/** + * DOC: execlist_submit_context tracepoint + * + * These tracepoint are used to track the contexts that are submitted to the + * ring. An mm switch is automatically performed by the GPU during the context + * switch. Given the fact that the mm switch is an important point in the + * lifetime of a vm, the vm assigned to the context is also printed by the + * tracepoint when full ppgtt is enabled. + */ +TRACE_EVENT(execlists_submit_context, + TP_PROTO(struct intel_engine_cs *ring, u32 to_num, struct intel_context *to), + + TP_ARGS(ring, to_num, to), + + TP_STRUCT__entry( + __field(u32, ring) + __field(u32, to_num) + __field(struct intel_context *, to) + __field(struct i915_address_space *, vm) + __field(u32, dev) + ), + + TP_fast_assign( + __entry->ring = ring->id; + __entry->to_num = to_num; + __entry->to = to; + __entry->vm = to->ppgtt ? &to->ppgtt->base : NULL; + __entry->dev = ring->dev->primary->index; + ), + + TP_printk("dev=%u, ring=%u, ctx%d=%p, ctx_vm=%p", + __entry->dev, __entry->ring, + __entry->to_num, __entry->to, __entry->vm) +); + #endif /* _I915_TRACE_H_ */ /* This part must be outside protection */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 6025ac7..e72759d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -135,6 +135,7 @@ #include <drm/drmP.h> #include <drm/i915_drm.h> #include "i915_drv.h" +#include "i915_trace.h" #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) @@ -367,6 +368,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, BUG_ON(!ctx_obj0); WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0)); + trace_execlists_submit_context(ring, 0, to0); execlists_ctx_write_tail(ctx_obj0, tail0); if (to1) { @@ -374,6 +376,7 @@ static void execlists_submit_contexts(struct intel_engine_cs *ring, BUG_ON(!ctx_obj1); WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1)); + trace_execlists_submit_context(ring, 1, to1); execlists_ctx_write_tail(ctx_obj1, tail1); }