| Message ID | 1416249574-22940-1-git-send-email-sviau@codeaurora.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
On Mon, Nov 17, 2014 at 1:39 PM, Stephane Viau <sviau@codeaurora.org> wrote: > The core clock rate depends on the hw configuration. Once we have > read the hardware revision, we can set the core clock to its > maximum value. > Before then, the clock is set at a rate supported by all MDP5 > revisions. > > Signed-off-by: Stephane Viau <sviau@codeaurora.org> Thanks, I have this queued up BR, -R > --- > drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 9 +++++---- > drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 3 ++- > 2 files changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c > index 1bb3a28..f2c15bd 100644 > --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c > +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c > @@ -62,6 +62,7 @@ static const struct mdp5_config msm8x74_config = { > .count = 4, > .base = { 0x12500, 0x12700, 0x12900, 0x12b00 }, > }, > + .max_clk = 200000000, > }; > > static const struct mdp5_config apq8084_config = { > @@ -99,6 +100,7 @@ static const struct mdp5_config apq8084_config = { > .count = 5, > .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 }, > }, > + .max_clk = 320000000, > }; > > struct mdp5_config_entry { > @@ -420,12 +422,13 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) > if (ret) > goto fail; > > - ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk); > - > ret = mdp5_select_hw_cfg(kms); > if (ret) > goto fail; > > + /* TODO: compute core clock rate at runtime */ > + clk_set_rate(mdp5_kms->src_clk, mdp5_kms->hw_cfg->max_clk); > + > /* make sure things are off before attaching iommu (bootloader could > * have left things on, in which case we'll start getting faults if > * we don't disable): > @@ -486,8 +489,6 @@ static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev) > /* TODO */ > #endif > config.iommu = iommu_domain_alloc(&platform_bus_type); > - /* TODO hard-coded in downstream mdss, but should it be? */ > - config.max_clk = 200000000; > /* TODO get from DT: */ > config.smp_blk_cnt = 22; > > diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h > index c91101d..bdbdcda 100644 > --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h > +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h > @@ -37,6 +37,8 @@ struct mdp5_config { > struct mdp5_sub_block dspp; > struct mdp5_sub_block ad; > struct mdp5_sub_block intf; > + > + uint32_t max_clk; > }; > extern const struct mdp5_config *mdp5_cfg; > #include "mdp5.xml.h" > @@ -78,7 +80,6 @@ struct mdp5_kms { > /* platform config data (ie. from DT, or pdata) */ > struct mdp5_platform_config { > struct iommu_domain *iommu; > - uint32_t max_clk; > int smp_blk_cnt; > }; > > -- > Qualcomm Innovation Center, Inc. > > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project >
diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c index 1bb3a28..f2c15bd 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c @@ -62,6 +62,7 @@ static const struct mdp5_config msm8x74_config = { .count = 4, .base = { 0x12500, 0x12700, 0x12900, 0x12b00 }, }, + .max_clk = 200000000, }; static const struct mdp5_config apq8084_config = { @@ -99,6 +100,7 @@ static const struct mdp5_config apq8084_config = { .count = 5, .base = { 0x12500, 0x12700, 0x12900, 0x12b00, 0x12d00 }, }, + .max_clk = 320000000, }; struct mdp5_config_entry { @@ -420,12 +422,13 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev) if (ret) goto fail; - ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk); - ret = mdp5_select_hw_cfg(kms); if (ret) goto fail; + /* TODO: compute core clock rate at runtime */ + clk_set_rate(mdp5_kms->src_clk, mdp5_kms->hw_cfg->max_clk); + /* make sure things are off before attaching iommu (bootloader could * have left things on, in which case we'll start getting faults if * we don't disable): @@ -486,8 +489,6 @@ static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev) /* TODO */ #endif config.iommu = iommu_domain_alloc(&platform_bus_type); - /* TODO hard-coded in downstream mdss, but should it be? */ - config.max_clk = 200000000; /* TODO get from DT: */ config.smp_blk_cnt = 22; diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h index c91101d..bdbdcda 100644 --- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h @@ -37,6 +37,8 @@ struct mdp5_config { struct mdp5_sub_block dspp; struct mdp5_sub_block ad; struct mdp5_sub_block intf; + + uint32_t max_clk; }; extern const struct mdp5_config *mdp5_cfg; #include "mdp5.xml.h" @@ -78,7 +80,6 @@ struct mdp5_kms { /* platform config data (ie. from DT, or pdata) */ struct mdp5_platform_config { struct iommu_domain *iommu; - uint32_t max_clk; int smp_blk_cnt; };
The core clock rate depends on the hw configuration. Once we have read the hardware revision, we can set the core clock to its maximum value. Before then, the clock is set at a rate supported by all MDP5 revisions. Signed-off-by: Stephane Viau <sviau@codeaurora.org> --- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.c | 9 +++++---- drivers/gpu/drm/msm/mdp/mdp5/mdp5_kms.h | 3 ++- 2 files changed, 7 insertions(+), 5 deletions(-)