From patchwork Tue Dec 9 18:17:20 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 5464461 Return-Path: X-Original-To: patchwork-linux-omap@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 15C3CBEEA8 for ; Tue, 9 Dec 2014 18:18:09 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 247CC20131 for ; Tue, 9 Dec 2014 18:18:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 2B731200E0 for ; Tue, 9 Dec 2014 18:18:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752024AbaLISSF (ORCPT ); Tue, 9 Dec 2014 13:18:05 -0500 Received: from comal.ext.ti.com ([198.47.26.152]:34088 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752005AbaLISSE (ORCPT ); Tue, 9 Dec 2014 13:18:04 -0500 Received: from dflxv15.itg.ti.com ([128.247.5.124]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id sB9IHLu9021312; Tue, 9 Dec 2014 12:17:21 -0600 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id sB9IHL5e023046; Tue, 9 Dec 2014 12:17:21 -0600 Received: from dlep33.itg.ti.com (157.170.170.75) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.174.1; Tue, 9 Dec 2014 12:17:20 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id sB9IHKeL019315; Tue, 9 Dec 2014 12:17:20 -0600 Date: Tue, 9 Dec 2014 12:17:20 -0600 From: Nishanth Menon To: Marc Zyngier CC: Benoit Cousson , Tony Lindgren , Santosh Shilimkar , "linux-arm-kernel@lists.infradead.org" , Stefan Agner , Jason Cooper , Thomas Gleixner , "linux-omap@vger.kernel.org" Subject: Re: [PATCH 0/5] irqchip: kill the GIC routable domain Message-ID: <20141209181719.GA2569@kahuna> References: <1417873576-10463-1-git-send-email-marc.zyngier@arm.com> <20141207171646.GA12049@kahuna> <20141207180322.GA15688@kahuna> <54856B21.6070104@arm.com> <20141208224116.GA2538@kahuna> <5486C6A6.8060702@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5486C6A6.8060702@arm.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-omap-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-omap@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On 09:53-20141209, Marc Zyngier wrote: > On 08/12/14 22:41, Nishanth Menon wrote: > > > Anyways.. The following diff[1] on top of your branch makes DRA7 work - I > > assume you will squash as needed and repost with linux-omap mailing list > > in CC. > > Brilliant. I'll squash that into my tree and repost at some point. K, it will be nice to have a reflow of the series based on v3.19-rc1 since there are dts dependencies and we dont want folks to have regressions on their platforms of choice.. Obviously, my tests are basic boot tests and should get a few weeks(as you already mentioned) on linux-next to get properly soaked > > > I increased the scope of testing knowing that WUGEN is present in many > > A9 based TI platforms as well.. and at least OMAP4 showed flakiness in > > my testing.. Also a few notes: > > > > Stuff like: am437x is a bit questionable (interrupt-parent probably should be wugen?) > > 175: 0 GIC 39 tps65218 > > > > OMAP5: (should be wugen?) > > 308: 4323 0 GIC 106 OMAP UART2 > > 411: 0 0 GIC 151 twl6040 > > 405: 1 0 GIC 39 palmas > > Well, I can't really tell. Someone with access to the documentation > should be able to find out. AM437x: http://www.ti.com/lit/pdf/spruhl7 OMAP5: http://www.ti.com/lit/pdf/swpu249 yeah, we should be able to do them as well - trivially since they follow the same structure as other SoCs without crossbar. > > > OMAP4 serial port is flaky -> not sure if it is due to routing of GIC to UART2 and not via WUGEN > > IRQ branch: with my fix applied: > > --------------------------------- > > [...] > > > 18: pandaboard-es: Boot FAIL: http://slexy.org/raw/s20ty0Z6i5 (not expected) > > 19: pandaboard-vanilla: Boot FAIL: http://slexy.org/raw/s20BYfaMd2 (not expected) > > If I read the log correctly, the serial port stops responding after a while? yeah - dug at the omap4 ones a bit, obviously once the deeper c states are hit, we'd like wakeupgen to wakeup CPU else we will be "sluggish" in the sense that the event is detected when some other wakeupgen enabled interrupt takes place. Adding the following makes my panda work fine. 1: pandaboard-es: Boot PASS: http://slexy.org/raw/s20o8DaBvh 2: pandaboard-vanilla: Boot PASS: http://slexy.org/raw/s222JndDdh diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi index 1505135..8b6d50e 100644 --- a/arch/arm/boot/dts/omap4-panda-common.dtsi +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi @@ -371,8 +371,8 @@ twl: twl@48 { reg = <0x48>; /* IRQ# = 7 */ - interrupts = ; /* IRQ_SYS_1N cascaded to gic */ - interrupt-parent = <&gic>; + interrupts = ; /* IRQ_SYS_1N cascaded to wakeupgen to gic */ + interrupt-parent = <&wakeupgen>; }; twl6040: twl@4b { @@ -383,8 +383,8 @@ pinctrl-0 = <&twl6040_pins>; /* IRQ# = 119 */ - interrupts = ; /* IRQ_SYS_2N cascaded to gic */ - interrupt-parent = <&gic>; + interrupts = ; /* IRQ_SYS_2N cascaded to wakeupgen to gic */ + interrupt-parent = <&wakeupgen>; ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */ vio-supply = <&v1v8>; @@ -479,17 +479,17 @@ }; &uart2 { - interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART2_RX>; }; &uart3 { - interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART3_RX>; }; &uart4 { - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH + interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH &omap4_pmx_core OMAP4_UART4_RX>; };