| Message ID | 1418208371-18851-2-git-send-email-lyz@rock-chips.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Hi, On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: > This patch to add a generic PHY driver for ROCKCHIP usb PHYs, > currently this driver can support RK3288. The RK3288 SoC have > three independent USB PHY IPs which are all configured through a > set of registers located in the GRF (general register files) > module. > > Signed-off-by: Yunzhi Li <lyz@rock-chips.com> > > --- > > Changes in v5: None > Changes in v4: > - Get number of PHYs from device tree. > - Model each PHY as subnode of the phy provider node. > > Changes in v3: > - Use BIT macro instead of bit shift ops. > - Rename the config entry to PHY_ROCKCHIP_USB. > > drivers/phy/Kconfig | 7 ++ > drivers/phy/Makefile | 1 + > drivers/phy/phy-rockchip-usb.c | 211 +++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 219 insertions(+) > create mode 100644 drivers/phy/phy-rockchip-usb.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index ccad880..8a39d2a 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA > depends on OF > select GENERIC_PHY > > +config PHY_ROCKCHIP_USB2 > + tristate "Rockchip USB2 PHY Driver" > + depends on ARCH_ROCKCHIP && OF > + select GENERIC_PHY > + help > + Enable this to support the Rockchip USB 2.0 PHY. > + > config PHY_ST_SPEAR1310_MIPHY > tristate "ST SPEAR1310-MIPHY driver" > select GENERIC_PHY > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index aa74f96..8a13f72 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o > phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o > obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o > obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o > +obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o > obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o > obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o > obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o > diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c > new file mode 100644 > index 0000000..0317c21 > --- /dev/null > +++ b/drivers/phy/phy-rockchip-usb.c > @@ -0,0 +1,211 @@ > +/* > + * Rockchip usb PHY driver > + * > + * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com> > + * Copyright (C) 2014 ROCKCHIP, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <linux/clk.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/mutex.h> > +#include <linux/of.h> > +#include <linux/of_address.h> > +#include <linux/phy/phy.h> > +#include <linux/platform_device.h> > +#include <linux/regulator/consumer.h> > +#include <linux/reset.h> > +#include <linux/regmap.h> > +#include <linux/mfd/syscon.h> > + > +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14) > + > +/* > + * The higher 16-bit of this register is used for write protection > + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. > + */ > +#define SIDDQ_MSK BIT(13 + 16) I think here the "MSK" is misleading. it should be something that refers write protection? > +#define SIDDQ_ON BIT(13) > +#define SIDDQ_OFF (0 << 13) > + > +struct rockchip_usb_phy { > + struct regmap *reg_base; > + unsigned int reg_offset; > + struct clk *clk; > + struct phy *phy; > + unsigned index; > +}; > + > +struct rockchip_usb_phy_priv { > + struct rockchip_usb_phy *phys; > + unsigned nphys; > +}; > + > +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, > + bool siddq) > +{ > + return regmap_write(phy->reg_base, phy->reg_offset, > + SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF)); Shouldn't we actually reset the bit for power off? > +} > + > +static int rockchip_usb_phy_power_off(struct phy *_phy) > +{ > + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); > + int ret = 0; > + > + /* Power down usb phy analog blocks by set siddq 1 */ > + ret = rockchip_usb_phy_power(phy, 1); > + if (ret) > + return ret; > + > + clk_disable_unprepare(phy->clk); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static int rockchip_usb_phy_power_on(struct phy *_phy) > +{ > + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); > + int ret = 0; > + > + ret = clk_prepare_enable(phy->clk); > + if (ret) > + return ret; > + > + /* Power up usb phy analog blocks by set siddq 0 */ > + ret = rockchip_usb_phy_power(phy, 0); > + if (ret) > + return ret; > + > + return 0; > +} > + > +static struct phy *rockchip_usb_phy_xlate(struct device *dev, > + struct of_phandle_args *args) > +{ > + struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev); > + int i; > + > + if (WARN_ON(args->args[0] >= priv->nphys)) > + return ERR_PTR(-ENODEV); > + > + for (i = 0; i < priv->nphys; i++) { > + if (priv->phys[i].index == args->args[0]) > + break; using the type of PHY instead of index might look better. However this shouldn't be needed at all if the phandle refers to the sub-node of the phy provider. Thanks Kishon
On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: > On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: > > diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c [] > > +/* > > + * The higher 16-bit of this register is used for write protection > > + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. > > + */ > > +#define SIDDQ_MSK BIT(13 + 16) huh? This #define looks _very_ odd. Is this supposed to be a single bit 29 or some range?
Hi, On Thursday 11 December 2014 11:42 AM, Joe Perches wrote: > On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: >> On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: >>> diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c > [] >>> +/* >>> + * The higher 16-bit of this register is used for write protection >>> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. >>> + */ >>> +#define SIDDQ_MSK BIT(13 + 16) > > huh? > > This #define looks _very_ odd. > > Is this supposed to be a single bit 29 or > some range? From what I understood, the most significant 16 bits are write locks to the least significant 16 bits. So If I have to write something on bit 0, I have to set bit 16. If I have to write something on bit 1, I have to set bit 17. If I have to write something on bit 2, I have to set bit 18. and so on. Thanks Kishon
On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: > Hi, > > On Thursday 11 December 2014 11:42 AM, Joe Perches wrote: > > On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: > >> On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: > >>> diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c > > [] > >>> +/* > >>> + * The higher 16-bit of this register is used for write protection > >>> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. > >>> + */ > >>> +#define SIDDQ_MSK BIT(13 + 16) > > > > huh? > > > > This #define looks _very_ odd. > > > > Is this supposed to be a single bit 29 or > > some range? > > From what I understood, the most significant 16 bits are write locks to the > least significant 16 bits. > > So If I have to write something on bit 0, I have to set bit 16. > If I have to write something on bit 1, I have to set bit 17. > If I have to write something on bit 2, I have to set bit 18. > and so on. To me it'd look better to use another << rather than a plus
On 2014/12/11 14:37, Joe Perches wrote: > On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Thursday 11 December 2014 11:42 AM, Joe Perches wrote: >>> On Thu, 2014-12-11 at 11:32 +0530, Kishon Vijay Abraham I wrote: >>>> On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: >>>>> diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c >>> [] >>>>> +/* >>>>> + * The higher 16-bit of this register is used for write protection >>>>> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. >>>>> + */ >>>>> +#define SIDDQ_MSK BIT(13 + 16) >>> huh? >>> >>> This #define looks _very_ odd. >>> >>> Is this supposed to be a single bit 29 or >>> some range? >> From what I understood, the most significant 16 bits are write locks to the >> least significant 16 bits. >> >> So If I have to write something on bit 0, I have to set bit 16. >> If I have to write something on bit 1, I have to set bit 17. >> If I have to write something on bit 2, I have to set bit 18. >> and so on. > To me it'd look better to use another << rather than a plus Like (BIT(13) << 16)? It looks strange, or could I just use ((1 << 13) << 16) to describe this bit ? --- Yunzhi Li @ rockchip
On Thu, 2014-12-11 at 14:52 +0800, Yunzhi Li wrote: > On 2014/12/11 14:37, Joe Perches wrote: > > On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: [] > >> So If I have to write something on bit 0, I have to set bit 16. > >> If I have to write something on bit 1, I have to set bit 17. > >> If I have to write something on bit 2, I have to set bit 18. > >> and so on. > > To me it'd look better to use another << rather than a plus > Like (BIT(13) << 16)? It looks strange, or could I just use ((1 << 13) > << 16) to describe this bit ? Up to you. To me, the BIT(x+y) seems odd.
On 12/11/2014 03:06 PM, Joe Perches wrote: > On Thu, 2014-12-11 at 14:52 +0800, Yunzhi Li wrote: >> On 2014/12/11 14:37, Joe Perches wrote: >>> On Thu, 2014-12-11 at 11:57 +0530, Kishon Vijay Abraham I wrote: > [] >>>> So If I have to write something on bit 0, I have to set bit 16. >>>> If I have to write something on bit 1, I have to set bit 17. >>>> If I have to write something on bit 2, I have to set bit 18. >>>> and so on. >>> To me it'd look better to use another << rather than a plus >> Like (BIT(13) << 16)? It looks strange, or could I just use ((1 << 13) >> << 16) to describe this bit ? > Up to you. To me, the BIT(x+y) seems odd. I think BIT(29) is better, since you have described in comments. > > > > >
Hi Kishon: On 2014/12/11 14:02, Kishon Vijay Abraham I wrote: > Hi, > > On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: >> This patch to add a generic PHY driver for ROCKCHIP usb PHYs, >> currently this driver can support RK3288. The RK3288 SoC have >> three independent USB PHY IPs which are all configured through a >> set of registers located in the GRF (general register files) >> module. >> >> Signed-off-by: Yunzhi Li <lyz@rock-chips.com> >> >> + >> +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14) >> + >> +/* >> + * The higher 16-bit of this register is used for write protection >> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. >> + */ >> +#define SIDDQ_MSK BIT(13 + 16) > I think here the "MSK" is misleading. it should be something that refers write > protection? So, #define SIDDQ_WRITE_ENA BIT(29) , could be ok ? >> +#define SIDDQ_ON BIT(13) >> +#define SIDDQ_OFF (0 << 13) >> + >> +struct rockchip_usb_phy { >> + struct regmap *reg_base; >> + unsigned int reg_offset; >> + struct clk *clk; >> + struct phy *phy; >> + unsigned index; >> +}; >> + >> +struct rockchip_usb_phy_priv { >> + struct rockchip_usb_phy *phys; >> + unsigned nphys; >> +}; >> + >> +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, >> + bool siddq) >> +{ >> + return regmap_write(phy->reg_base, phy->reg_offset, >> + SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF)); > Shouldn't we actually reset the bit for power off? Sorry, which bit you refer to here and why should it be reset? could you give more infomation. --- Yunzhi Li @ rockchip
Hi, On Thursday 11 December 2014 01:14 PM, Yunzhi Li wrote: > Hi Kishon: > > On 2014/12/11 14:02, Kishon Vijay Abraham I wrote: >> Hi, >> >> On Wednesday 10 December 2014 04:16 PM, Yunzhi Li wrote: >>> This patch to add a generic PHY driver for ROCKCHIP usb PHYs, >>> currently this driver can support RK3288. The RK3288 SoC have >>> three independent USB PHY IPs which are all configured through a >>> set of registers located in the GRF (general register files) >>> module. >>> >>> Signed-off-by: Yunzhi Li <lyz@rock-chips.com> >>> >>> + >>> +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14) >>> + >>> +/* >>> + * The higher 16-bit of this register is used for write protection >>> + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. >>> + */ >>> +#define SIDDQ_MSK BIT(13 + 16) >> I think here the "MSK" is misleading. it should be something that refers write >> protection? > So, #define SIDDQ_WRITE_ENA BIT(29) , could be ok ? yeah. should be fine. >>> +#define SIDDQ_ON BIT(13) >>> +#define SIDDQ_OFF (0 << 13) >>> + >>> +struct rockchip_usb_phy { >>> + struct regmap *reg_base; >>> + unsigned int reg_offset; >>> + struct clk *clk; >>> + struct phy *phy; >>> + unsigned index; >>> +}; >>> + >>> +struct rockchip_usb_phy_priv { >>> + struct rockchip_usb_phy *phys; >>> + unsigned nphys; >>> +}; >>> + >>> +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, >>> + bool siddq) >>> +{ >>> + return regmap_write(phy->reg_base, phy->reg_offset, >>> + SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF)); >> Shouldn't we actually reset the bit for power off? > Sorry, which bit you refer to here and why should it be reset? could you give > more infomation. Never mind. Initially was thinking it might affect bits other than siddq but anyway you have write lock. So should be fine. Thanks Kishon
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index ccad880..8a39d2a 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -239,6 +239,13 @@ config PHY_QCOM_IPQ806X_SATA depends on OF select GENERIC_PHY +config PHY_ROCKCHIP_USB2 + tristate "Rockchip USB2 PHY Driver" + depends on ARCH_ROCKCHIP && OF + select GENERIC_PHY + help + Enable this to support the Rockchip USB 2.0 PHY. + config PHY_ST_SPEAR1310_MIPHY tristate "ST SPEAR1310-MIPHY driver" select GENERIC_PHY diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index aa74f96..8a13f72 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,6 +28,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o +obj-$(CONFIG_PHY_ROCKCHIP_USB2) += phy-rockchip-usb.o obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o diff --git a/drivers/phy/phy-rockchip-usb.c b/drivers/phy/phy-rockchip-usb.c new file mode 100644 index 0000000..0317c21 --- /dev/null +++ b/drivers/phy/phy-rockchip-usb.c @@ -0,0 +1,211 @@ +/* + * Rockchip usb PHY driver + * + * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com> + * Copyright (C) 2014 ROCKCHIP, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/of_address.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regulator/consumer.h> +#include <linux/reset.h> +#include <linux/regmap.h> +#include <linux/mfd/syscon.h> + +#define ROCKCHIP_RK3288_UOC(n) (0x320 + n * 0x14) + +/* + * The higher 16-bit of this register is used for write protection + * only if BIT(13 + 16) set to 1 the BIT(13) can be written. + */ +#define SIDDQ_MSK BIT(13 + 16) +#define SIDDQ_ON BIT(13) +#define SIDDQ_OFF (0 << 13) + +struct rockchip_usb_phy { + struct regmap *reg_base; + unsigned int reg_offset; + struct clk *clk; + struct phy *phy; + unsigned index; +}; + +struct rockchip_usb_phy_priv { + struct rockchip_usb_phy *phys; + unsigned nphys; +}; + +static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy, + bool siddq) +{ + return regmap_write(phy->reg_base, phy->reg_offset, + SIDDQ_MSK | (siddq ? SIDDQ_ON : SIDDQ_OFF)); +} + +static int rockchip_usb_phy_power_off(struct phy *_phy) +{ + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); + int ret = 0; + + /* Power down usb phy analog blocks by set siddq 1 */ + ret = rockchip_usb_phy_power(phy, 1); + if (ret) + return ret; + + clk_disable_unprepare(phy->clk); + if (ret) + return ret; + + return 0; +} + +static int rockchip_usb_phy_power_on(struct phy *_phy) +{ + struct rockchip_usb_phy *phy = phy_get_drvdata(_phy); + int ret = 0; + + ret = clk_prepare_enable(phy->clk); + if (ret) + return ret; + + /* Power up usb phy analog blocks by set siddq 0 */ + ret = rockchip_usb_phy_power(phy, 0); + if (ret) + return ret; + + return 0; +} + +static struct phy *rockchip_usb_phy_xlate(struct device *dev, + struct of_phandle_args *args) +{ + struct rockchip_usb_phy_priv *priv = dev_get_drvdata(dev); + int i; + + if (WARN_ON(args->args[0] >= priv->nphys)) + return ERR_PTR(-ENODEV); + + for (i = 0; i < priv->nphys; i++) { + if (priv->phys[i].index == args->args[0]) + break; + } + + if (i == priv->nphys) + return ERR_PTR(-ENODEV); + + return priv->phys[i].phy; +} + +static struct phy_ops ops = { + .power_on = rockchip_usb_phy_power_on, + .power_off = rockchip_usb_phy_power_off, + .owner = THIS_MODULE, +}; + +static int rockchip_usb_phy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rockchip_usb_phy *rk_phy; + struct rockchip_usb_phy_priv *priv; + struct phy_provider *phy_provider; + struct device_node *child; + struct regmap *grf; + unsigned int phy_id; + + grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + if (IS_ERR(grf)) { + dev_err(&pdev->dev, "Missing rockchip,grf property\n"); + return PTR_ERR(grf); + } + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* Get number of phys from device tree */ + priv->nphys = of_get_child_count(dev->of_node); + if (priv->nphys == 0) + return -ENODEV; + + priv->phys = devm_kzalloc(dev, priv->nphys * sizeof(*priv->phys), + GFP_KERNEL); + if (!priv->phys) + return -ENOMEM; + + rk_phy = priv->phys; + for_each_available_child_of_node(dev->of_node, child) { + if (of_property_read_u32(child, "reg", &phy_id)) { + dev_err(dev, "missing reg property in node %s\n", + child->name); + return -EINVAL; + } + + if (phy_id < 0 || phy_id >= priv->nphys) { + dev_err(dev, "invalid phy id\n"); + return -EINVAL; + } + + rk_phy->reg_offset = ROCKCHIP_RK3288_UOC(phy_id); + rk_phy->reg_base = grf; + + rk_phy->clk = of_clk_get(child, 0); + if (IS_ERR(rk_phy->clk)) { + dev_warn(dev, "failed to get clock\n"); + rk_phy->clk = NULL; + } + + rk_phy->phy = devm_phy_create(dev, NULL, &ops); + if (IS_ERR(rk_phy->phy)) { + dev_err(dev, "failed to create PHY %d\n", phy_id); + return PTR_ERR(rk_phy->phy); + } + phy_set_drvdata(rk_phy->phy, rk_phy); + + rk_phy->index = phy_id; + rk_phy++; + } + + platform_set_drvdata(pdev, priv); + + phy_provider = devm_of_phy_provider_register(dev, + rockchip_usb_phy_xlate); + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id rockchip_usb_phy_dt_ids[] = { + { .compatible = "rockchip,rk3288-usb-phy" }, + {} +}; + +MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids); + +static struct platform_driver rockchip_usb_driver = { + .probe = rockchip_usb_phy_probe, + .driver = { + .name = "rockchip-usb-phy", + .owner = THIS_MODULE, + .of_match_table = rockchip_usb_phy_dt_ids, + }, +}; + +module_platform_driver(rockchip_usb_driver); + +MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>"); +MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver"); +MODULE_LICENSE("GPL v2");
This patch to add a generic PHY driver for ROCKCHIP usb PHYs, currently this driver can support RK3288. The RK3288 SoC have three independent USB PHY IPs which are all configured through a set of registers located in the GRF (general register files) module. Signed-off-by: Yunzhi Li <lyz@rock-chips.com> --- Changes in v5: None Changes in v4: - Get number of PHYs from device tree. - Model each PHY as subnode of the phy provider node. Changes in v3: - Use BIT macro instead of bit shift ops. - Rename the config entry to PHY_ROCKCHIP_USB. drivers/phy/Kconfig | 7 ++ drivers/phy/Makefile | 1 + drivers/phy/phy-rockchip-usb.c | 211 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 219 insertions(+) create mode 100644 drivers/phy/phy-rockchip-usb.c