[1/4] pinctrl: qcom: Add multiple copy base support
diff mbox

Message ID 1418936395-14623-2-git-send-email-agross@codeaurora.org
State Under Review, archived
Delegated to: Andy Gross
Headers show

Commit Message

Andy Gross Dec. 18, 2014, 8:59 p.m. UTC
Qualcomm pinctrl devices support functions that can be routed to multiple pins.
In some cases, there are additional mux registers that must be set for the pins
to work correctly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c |   10 ++++++++++
 drivers/pinctrl/qcom/pinctrl-msm.h |    4 ++++
 2 files changed, 14 insertions(+)

Comments

Bjorn Jan. 26, 2015, 10:26 p.m. UTC | #1
On Thu 18 Dec 12:59 PST 2014, Andy Gross wrote:

> Qualcomm pinctrl devices support functions that can be routed to multiple pins.
> In some cases, there are additional mux registers that must be set for the pins
> to work correctly.
> 

I've described it as "second level muxing", but your description works too...

[..]

> +	/*
> +	 * if an alternate copy configuration is required, configure the pins to
> +	 * steer the function to the correct set of pins.  This is used in cases
> +	 * where we have more than one copy of the pins for a function
> +	 */
> +	if (f->requires_copy_select)
> +		writel(f->copy_select_value, pctrl->regs + f->copy_select_reg);

I'm not sure if this is sufficient.

In the APQ8064 case (patch 3) you use this to write 0 or 1 to $2074, but if I
read the documentation correctly you should also write to $207c and $2080 to
enable/disable slew rate control of the individual paths.

On 8974 we don't have the muxing, but the documentation states that we should
set bit 0 of $2030 depending on slimbus being muxed or not. (not sure what to
do about bit 1 though)


I looked at assigning an optional function pointer to the function, that way we
could easily express the platform specific tweaks in the individual drivers.

However, as the muxing is deselected we need to make sure the slew rate is
disabled and the only sane way I can think of then would be to tie this to the
pingroup, as selecting any other entry from the pingroup should trigger the
reset.

Regards,
Bjorn
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Patch
diff mbox

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index e730935..17e2867 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -141,11 +141,13 @@  static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 {
 	struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 	const struct msm_pingroup *g;
+	const struct msm_function *f;
 	unsigned long flags;
 	u32 val;
 	int i;
 
 	g = &pctrl->soc->groups[group];
+	f = &pctrl->soc->functions[function];
 
 	for (i = 0; i < g->nfuncs; i++) {
 		if (g->funcs[i] == function)
@@ -162,6 +164,14 @@  static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
 	val |= i << g->mux_bit;
 	writel(val, pctrl->regs + g->ctl_reg);
 
+	/*
+	 * if an alternate copy configuration is required, configure the pins to
+	 * steer the function to the correct set of pins.  This is used in cases
+	 * where we have more than one copy of the pins for a function
+	 */
+	if (f->requires_copy_select)
+		writel(f->copy_select_value, pctrl->regs + f->copy_select_reg);
+
 	spin_unlock_irqrestore(&pctrl->lock, flags);
 
 	return 0;
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index b952c4b..7180587 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -25,6 +25,10 @@  struct msm_function {
 	const char *name;
 	const char * const *groups;
 	unsigned ngroups;
+
+	unsigned requires_copy_select;
+	unsigned copy_select_reg;
+	unsigned copy_select_value;
 };
 
 /**