[3/4] drm/i915: Use frame buffer modifiers for tiled display
diff mbox

Message ID 1423147315-23890-4-git-send-email-tvrtko.ursulin@linux.intel.com
State New, archived
Headers show

Commit Message

Tvrtko Ursulin Feb. 5, 2015, 2:41 p.m. UTC
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Start using frame buffer modifiers instead of object tiling mode
for display purposes.

To ensure compatibility with old userspace which is using set_tiling
and does not know about frame buffer modifiers, the latter are faked
internally when tile object is set for display. This way all interested
call sites can use fb modifiers exclusively.

Also ensure tiling specified via fb modifiers must match object tiling
used for fencing if both are specified.

v2:
   * Refactored to use fb modifiers directly in switch statements in
     order to completely disconnect from the object tiling namespace.
     (Daniel Vetter)
   * Added helper to convert to hardware mode representation for
     future proofing.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 150 +++++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_drv.h     |   9 ++-
 drivers/gpu/drm/i915/intel_pm.c      |   7 +-
 drivers/gpu/drm/i915/intel_sprite.c  |  34 ++++----
 4 files changed, 124 insertions(+), 76 deletions(-)

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e5c0579..cf64e3c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2190,14 +2190,31 @@  static bool need_vtd_wa(struct drm_device *dev)
 }
 
 int
-intel_fb_align_height(struct drm_device *dev, int height, unsigned int tiling)
+intel_fb_align_height(struct drm_device *dev, int height, u64 tiling)
 {
 	int tile_height;
 
-	tile_height = tiling ? (IS_GEN2(dev) ? 16 : 8) : 1;
+	tile_height = tiling != I915_FORMAT_MOD_NONE ?
+					(IS_GEN2(dev) ? 16 : 8) : 1;
 	return ALIGN(height, tile_height);
 }
 
+static u64 intel_fb_modifier_tiling(u64 mod)
+{
+	return mod & I915_FORMAT_MOD_TILING_MASK;
+}
+
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb)
+{
+	return fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK;
+}
+
+static u32 intel_fb_tiling_hw_mode(struct drm_framebuffer *fb)
+{
+	return (fb->modifier[0] & I915_FORMAT_MOD_TILING_MASK) !=
+	       I915_FORMAT_MOD_NONE ? 1 : 0;
+}
+
 int
 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			   struct drm_framebuffer *fb,
@@ -2211,8 +2228,8 @@  intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
@@ -2222,7 +2239,7 @@  intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 		else
 			alignment = 64 * 1024;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		if (INTEL_INFO(dev)->gen >= 9)
 			alignment = 256 * 1024;
 		else {
@@ -2230,11 +2247,9 @@  intel_pin_and_fence_fb_obj(struct drm_plane *plane,
 			alignment = 0;
 		}
 		break;
-	case I915_TILING_Y:
-		WARN(1, "Y tiled bo slipped through, driver bug!\n");
-		return -EINVAL;
 	default:
-		BUG();
+		MISSING_CASE(intel_fb_tiling_mode(fb));
+		return -EINVAL;
 	}
 
 	/* Note that the w/a also requires 64 PTE of padding following the
@@ -2293,11 +2308,11 @@  void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
  * is assumed to be a power-of-two. */
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int cpp,
 					     unsigned int pitch)
 {
-	if (tiling_mode != I915_TILING_NONE) {
+	if (tiling_mode != I915_FORMAT_MOD_NONE) {
 		unsigned int tile_rows, tiles;
 
 		tile_rows = *y / 8;
@@ -2381,14 +2396,17 @@  intel_alloc_plane_obj(struct intel_crtc *crtc,
 	if (!obj)
 		return false;
 
-	obj->tiling_mode = plane_config->tiling;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (plane_config->tiling == I915_FORMAT_MOD_X_TILED) {
+		obj->tiling_mode = I915_TILING_X;
 		obj->stride = crtc->base.primary->fb->pitches[0];
+	}
 
 	mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
 	mode_cmd.width = crtc->base.primary->fb->width;
 	mode_cmd.height = crtc->base.primary->fb->height;
+	mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
 	mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
+	mode_cmd.modifier[0] = plane_config->tiling;
 
 	mutex_lock(&dev->struct_mutex);
 
@@ -2461,7 +2479,8 @@  intel_find_plane_obj(struct intel_crtc *intel_crtc,
 			continue;
 
 		if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
-			if (obj->tiling_mode != I915_TILING_NONE)
+			if (intel_fb_tiling_mode(c->primary->fb) !=
+			    I915_FORMAT_MOD_NONE)
 				dev_priv->preserve_bios_swizzle = true;
 
 			drm_framebuffer_reference(c->primary->fb);
@@ -2487,6 +2506,7 @@  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2558,8 +2578,7 @@  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (INTEL_INFO(dev)->gen >= 4 &&
-	    obj->tiling_mode != I915_TILING_NONE)
+	if (INTEL_INFO(dev)->gen >= 4 && tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (IS_G4X(dev))
@@ -2569,7 +2588,7 @@  static void i9xx_update_primary_plane(struct drm_crtc *crtc,
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		intel_crtc->dspaddr_offset =
-			intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+			intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 						       pixel_size,
 						       fb->pitches[0]);
 		linear_offset -= intel_crtc->dspaddr_offset;
@@ -2619,6 +2638,7 @@  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 	u32 dspcntr;
 	u32 reg = DSPCNTR(plane);
 	int pixel_size;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	if (!intel_crtc->primary_enabled) {
 		I915_WRITE(reg, 0);
@@ -2667,7 +2687,7 @@  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 		BUG();
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 
 	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
@@ -2675,7 +2695,7 @@  static void ironlake_update_primary_plane(struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	intel_crtc->dspaddr_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size,
 					       fb->pitches[0]);
 	linear_offset -= intel_crtc->dspaddr_offset;
@@ -2763,11 +2783,11 @@  static void skylake_update_primary_plane(struct drm_crtc *crtc,
 	 * The stride is either expressed as a multiple of 64 bytes chunks for
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -6613,9 +6633,10 @@  i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(plane));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -6623,7 +6644,7 @@  i9xx_get_initial_plane_config(struct intel_crtc *crtc,
 	fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
 
 	if (INTEL_INFO(dev)->gen >= 4) {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(plane));
 		else
 			offset = I915_READ(DSPLINOFF(plane));
@@ -7646,7 +7667,9 @@  skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_CTL(pipe, 0));
 	if (val & PLANE_CTL_TILED_MASK)
-		plane_config->tiling = I915_TILING_X;
+		plane_config->tiling = I915_FORMAT_MOD_X_TILED;
+	else
+		plane_config->tiling = I915_FORMAT_MOD_NONE;
 
 	pixel_format = val & PLANE_CTL_FORMAT_MASK;
 	fourcc = skl_format_to_fourcc(pixel_format,
@@ -7666,10 +7689,10 @@  skylake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(PLANE_STRIDE(pipe, 0));
 	switch (plane_config->tiling) {
-	case I915_TILING_NONE:
+	case I915_FORMAT_MOD_NONE:
 		stride_mult = 64;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride_mult = 512;
 		break;
 	default:
@@ -7743,9 +7766,10 @@  ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 
 	val = I915_READ(DSPCNTR(pipe));
 
+	plane_config->tiling = I915_FORMAT_MOD_NONE;
 	if (INTEL_INFO(dev)->gen >= 4)
 		if (val & DISPPLANE_TILED)
-			plane_config->tiling = I915_TILING_X;
+			plane_config->tiling = I915_FORMAT_MOD_X_TILED;
 
 	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
 	fourcc = i9xx_format_to_fourcc(pixel_format);
@@ -7756,7 +7780,7 @@  ironlake_get_initial_plane_config(struct intel_crtc *crtc,
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
 		offset = I915_READ(DSPOFFSET(pipe));
 	} else {
-		if (plane_config->tiling)
+		if (plane_config->tiling != I915_FORMAT_MOD_NONE)
 			offset = I915_READ(DSPTILEOFF(pipe));
 		else
 			offset = I915_READ(DSPLINOFF(pipe));
@@ -9307,7 +9331,7 @@  static int intel_gen4_queue_flip(struct drm_device *dev,
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
 	intel_ring_emit(ring, fb->pitches[0]);
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
-			obj->tiling_mode);
+			intel_fb_tiling_hw_mode(fb));
 
 	/* XXX Enabling the panel-fitter across page-flip is so far
 	 * untested on non-native modes, so ignore it for now.
@@ -9340,7 +9364,7 @@  static int intel_gen6_queue_flip(struct drm_device *dev,
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP |
 			MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
-	intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
+	intel_ring_emit(ring, fb->pitches[0] | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	/* Contrary to the suggestions in the documentation,
@@ -9444,7 +9468,7 @@  static int intel_gen7_queue_flip(struct drm_device *dev,
 	}
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
-	intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
+	intel_ring_emit(ring, (fb->pitches[0] | intel_fb_tiling_hw_mode(fb)));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 	intel_ring_emit(ring, (MI_NOOP));
 
@@ -9485,14 +9509,13 @@  static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
-	struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
 	const enum pipe pipe = intel_crtc->pipe;
 	u32 ctl, stride;
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	ctl = I915_READ(PLANE_CTL(pipe, 0));
 	ctl &= ~PLANE_CTL_TILED_MASK;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		ctl |= PLANE_CTL_TILED_X;
 
 	/*
@@ -9500,7 +9523,7 @@  static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
 	 * linear buffers or in number of tiles for tiled buffers.
 	 */
 	stride = fb->pitches[0] >> 6;
-	if (obj->tiling_mode == I915_TILING_X)
+	if (tiling_mode == I915_FORMAT_MOD_X_TILED)
 		stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
 
 	/*
@@ -9518,16 +9541,14 @@  static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
 {
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = dev->dev_private;
-	struct intel_framebuffer *intel_fb =
-		to_intel_framebuffer(intel_crtc->base.primary->fb);
-	struct drm_i915_gem_object *obj = intel_fb->obj;
+	struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
 	u32 dspcntr;
 	u32 reg;
 
 	reg = DSPCNTR(intel_crtc->plane);
 	dspcntr = I915_READ(reg);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE)
 		dspcntr |= DISPPLANE_TILED;
 	else
 		dspcntr &= ~DISPPLANE_TILED;
@@ -9627,11 +9648,11 @@  static int intel_gen9_queue_flip(struct drm_device *dev,
 		return -ENODEV;
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		stride = fb->pitches[0] >> 9;
 		break;
 	default:
@@ -9655,7 +9676,7 @@  static int intel_gen9_queue_flip(struct drm_device *dev,
 	intel_ring_emit(ring, 0);
 
 	intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane);
-	intel_ring_emit(ring, stride << 6 | obj->tiling_mode);
+	intel_ring_emit(ring, stride << 6 | intel_fb_tiling_hw_mode(fb));
 	intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
 
 	intel_mark_page_flip_active(intel_crtc);
@@ -9831,7 +9852,8 @@  static int intel_crtc_page_flip(struct drm_crtc *crtc,
 
 	if (IS_VALLEYVIEW(dev)) {
 		ring = &dev_priv->ring[BCS];
-		if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
+		if (intel_fb_tiling_mode(fb) !=
+		    intel_fb_tiling_mode(work->old_fb))
 			/* vlv: DISPLAY_FLIP fails to change tiling */
 			ring = NULL;
 	} else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
@@ -12208,7 +12230,8 @@  intel_check_cursor_plane(struct drm_plane *plane,
 
 	/* we only need to pin inside GTT if cursor is non-phy */
 	mutex_lock(&dev->struct_mutex);
-	if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
+	if (!INTEL_INFO(dev)->cursor_needs_physical &&
+	    intel_fb_tiling_mode(fb) != I915_FORMAT_MOD_NONE) {
 		DRM_DEBUG_KMS("cursor cannot be tiled\n");
 		ret = -EINVAL;
 	}
@@ -12689,6 +12712,7 @@  static int intel_framebuffer_init(struct drm_device *dev,
 {
 	int aligned_height;
 	int pitch_limit;
+	u64 tiling_mode = I915_FORMAT_MOD_NONE;
 	int ret;
 
 	WARN_ON(!mutex_is_locked(&dev->struct_mutex));
@@ -12698,6 +12722,29 @@  static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 	}
 
+	/* If obj is tiled and fb modifier not set propagate it in
+	 * for backward compatibility with old userspace.
+	 */
+	if (obj->tiling_mode && !(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) {
+		tiling_mode = mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
+	}
+
+	/* Get tiling mode from fb modifier if set. */
+	if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS)
+		tiling_mode = intel_fb_modifier_tiling(mode_cmd->modifier[0]);
+	else
+		mode_cmd->modifier[0] = tiling_mode;
+
+	/* Ensure new userspace is using the interface correctly by only
+	 * allowing old usage of set_tiling if it matches with the
+	 * fb modifier tiling.
+	 */
+	if (obj->tiling_mode && tiling_mode != I915_FORMAT_MOD_X_TILED) {
+		DRM_ERROR("Object (%u) and fb (%llx) tiling mismatch!\n",
+			  obj->tiling_mode, tiling_mode);
+		return -EINVAL;
+	}
+
 	if (mode_cmd->pitches[0] & 63) {
 		DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
 			  mode_cmd->pitches[0]);
@@ -12707,12 +12754,12 @@  static int intel_framebuffer_init(struct drm_device *dev,
 	if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
 		pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 4) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 16*1024;
 		else
 			pitch_limit = 32*1024;
 	} else if (INTEL_INFO(dev)->gen >= 3) {
-		if (obj->tiling_mode)
+		if (tiling_mode)
 			pitch_limit = 8*1024;
 		else
 			pitch_limit = 16*1024;
@@ -12722,12 +12769,13 @@  static int intel_framebuffer_init(struct drm_device *dev,
 
 	if (mode_cmd->pitches[0] > pitch_limit) {
 		DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
-			  obj->tiling_mode ? "tiled" : "linear",
+			  tiling_mode != I915_FORMAT_MOD_NONE ?
+				"tiled" : "linear",
 			  mode_cmd->pitches[0], pitch_limit);
 		return -EINVAL;
 	}
 
-	if (obj->tiling_mode != I915_TILING_NONE &&
+	if (tiling_mode != I915_FORMAT_MOD_NONE && obj->stride &&
 	    mode_cmd->pitches[0] != obj->stride) {
 		DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
 			  mode_cmd->pitches[0], obj->stride);
@@ -12782,7 +12830,7 @@  static int intel_framebuffer_init(struct drm_device *dev,
 		return -EINVAL;
 
 	aligned_height = intel_fb_align_height(dev, mode_cmd->height,
-					       obj->tiling_mode);
+					       tiling_mode);
 	/* FIXME drm helper for size checks (especially planar formats)? */
 	if (obj->base.size < aligned_height * mode_cmd->pitches[0])
 		return -EINVAL;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f048f8b..f96dc51 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -258,7 +258,7 @@  struct intel_plane_state {
 };
 
 struct intel_initial_plane_config {
-	unsigned int tiling;
+	u64 tiling;
 	int size;
 	u32 base;
 };
@@ -877,8 +877,7 @@  void intel_frontbuffer_flip(struct drm_device *dev,
 	intel_frontbuffer_flush(dev, frontbuffer_bits);
 }
 
-int intel_fb_align_height(struct drm_device *dev, int height,
-			  unsigned int tiling);
+int intel_fb_align_height(struct drm_device *dev, int height, u64 tiling);
 void intel_fb_obj_flush(struct drm_i915_gem_object *obj, bool retire);
 
 
@@ -984,7 +983,7 @@  void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
 #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
 #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
-					     unsigned int tiling_mode,
+					     u64 tiling_mode,
 					     unsigned int bpp,
 					     unsigned int pitch);
 void intel_prepare_reset(struct drm_device *dev);
@@ -1008,6 +1007,8 @@  void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc);
 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file);
 
+u64 intel_fb_tiling_mode(struct drm_framebuffer *fb);
+
 /* intel_dp.c */
 void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index bebefe7..db82184 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1182,12 +1182,9 @@  static void i9xx_update_wm(struct drm_crtc *unused_crtc)
 	DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
 
 	if (IS_I915GM(dev) && enabled) {
-		struct drm_i915_gem_object *obj;
-
-		obj = intel_fb_obj(enabled->primary->fb);
-
 		/* self-refresh seems busted with untiled */
-		if (obj->tiling_mode == I915_TILING_NONE)
+		if (intel_fb_tiling_mode(enabled->primary->fb) ==
+		    I915_FORMAT_MOD_NONE)
 			enabled = NULL;
 	}
 
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0a52c44..c64e854 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -245,11 +245,11 @@  skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
 		BUG();
 	}
 
-	switch (obj->tiling_mode) {
-	case I915_TILING_NONE:
+	switch (intel_fb_tiling_mode(fb)) {
+	case I915_FORMAT_MOD_NONE:
 		stride = fb->pitches[0] >> 6;
 		break;
-	case I915_TILING_X:
+	case I915_FORMAT_MOD_X_TILED:
 		plane_ctl |= PLANE_CTL_TILED_X;
 		stride = fb->pitches[0] >> 9;
 		break;
@@ -413,6 +413,7 @@  vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	u32 sprctl;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPCNTR(pipe, plane));
 
@@ -471,7 +472,7 @@  vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SP_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SP_TILED;
 
 	sprctl |= SP_ENABLE;
@@ -488,7 +489,7 @@  vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
-							obj->tiling_mode,
+							tiling_mode,
 							pixel_size,
 							fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
@@ -509,7 +510,7 @@  vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
 	I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
 	I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
 	else
 		I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
@@ -613,6 +614,7 @@  ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	u32 sprctl, sprscale = 0;
 	unsigned long sprsurf_offset, linear_offset;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	sprctl = I915_READ(SPRCTL(pipe));
 
@@ -652,7 +654,7 @@  ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	sprctl |= SPRITE_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		sprctl |= SPRITE_TILED;
 
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
@@ -680,7 +682,7 @@  ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	sprsurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= sprsurf_offset;
 
@@ -705,7 +707,7 @@  ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 * register */
 	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
 		I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
-	else if (obj->tiling_mode != I915_TILING_NONE)
+	else if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(SPRLINOFF(pipe), linear_offset);
@@ -818,6 +820,7 @@  ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	unsigned long dvssurf_offset, linear_offset;
 	u32 dvscntr, dvsscale;
 	int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
+	u64 tiling_mode = intel_fb_tiling_mode(fb);
 
 	dvscntr = I915_READ(DVSCNTR(pipe));
 
@@ -857,7 +860,7 @@  ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	 */
 	dvscntr |= DVS_GAMMA_ENABLE;
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		dvscntr |= DVS_TILED;
 
 	if (IS_GEN6(dev))
@@ -880,7 +883,7 @@  ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 
 	linear_offset = y * fb->pitches[0] + x * pixel_size;
 	dvssurf_offset =
-		intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
+		intel_gen4_compute_page_offset(&x, &y, tiling_mode,
 					       pixel_size, fb->pitches[0]);
 	linear_offset -= dvssurf_offset;
 
@@ -897,7 +900,7 @@  ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 	I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
 	I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
 
-	if (obj->tiling_mode != I915_TILING_NONE)
+	if (tiling_mode != I915_FORMAT_MOD_NONE)
 		I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
 	else
 		I915_WRITE(DVSLINOFF(pipe), linear_offset);
@@ -1076,7 +1079,6 @@  intel_check_sprite_plane(struct drm_plane *plane,
 	struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
 	struct intel_plane *intel_plane = to_intel_plane(plane);
 	struct drm_framebuffer *fb = state->base.fb;
-	struct drm_i915_gem_object *obj = intel_fb_obj(fb);
 	int crtc_x, crtc_y;
 	unsigned int crtc_w, crtc_h;
 	uint32_t src_x, src_y, src_w, src_h;
@@ -1107,9 +1109,9 @@  intel_check_sprite_plane(struct drm_plane *plane,
 	}
 
 	/* Sprite planes can be linear or x-tiled surfaces */
-	switch (obj->tiling_mode) {
-		case I915_TILING_NONE:
-		case I915_TILING_X:
+	switch (intel_fb_tiling_mode(fb)) {
+		case I915_FORMAT_MOD_NONE:
+		case I915_FORMAT_MOD_X_TILED:
 			break;
 		default:
 			DRM_DEBUG_KMS("Unsupported tiling mode\n");