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[1/2] drm/radeon: workaround for CP HW bug on CIK

Message ID 1423574800-29627-1-git-send-email-deathsimple@vodafone.de (mailing list archive)
State New, archived
Headers show

Commit Message

Christian König Feb. 10, 2015, 1:26 p.m. UTC 
From: Christian König <christian.koenig@amd.com>

Emit the EOP twice to avoid cache flushing problems.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
---
 drivers/gpu/drm/radeon/cik.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

Comments

Alex Deucher Feb. 10, 2015, 3:06 p.m. UTC | #1 
On Tue, Feb 10, 2015 at 8:26 AM, Christian König
<deathsimple@vodafone.de> wrote:
> From: Christian König <christian.koenig@amd.com>
>
> Emit the EOP twice to avoid cache flushing problems.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> Cc: stable@vger.kernel.org

Applied.  Thanks!

Alex

> ---
>  drivers/gpu/drm/radeon/cik.c | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index de77c27..5594416 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -3905,7 +3905,21 @@ void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
>         struct radeon_ring *ring = &rdev->ring[fence->ring];
>         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
>
> -       /* EVENT_WRITE_EOP - flush caches, send int */
> +       /* Workaround for cache flush problems. First send a dummy EOP
> +        * event down the pipe with seq one below.
> +        */
> +       radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
> +       radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
> +                                EOP_TC_ACTION_EN |
> +                                EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
> +                                EVENT_INDEX(5)));
> +       radeon_ring_write(ring, addr & 0xfffffffc);
> +       radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
> +                               DATA_SEL(1) | INT_SEL(0));
> +       radeon_ring_write(ring, fence->seq - 1);
> +       radeon_ring_write(ring, 0);
> +
> +       /* Then send the real EOP event down the pipe. */
>         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
>         radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
>                                  EOP_TC_ACTION_EN |
> --
> 1.9.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
diff mbox

Patch

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index de77c27..5594416 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3905,7 +3905,21 @@  void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
 	struct radeon_ring *ring = &rdev->ring[fence->ring];
 	u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
 
-	/* EVENT_WRITE_EOP - flush caches, send int */
+	/* Workaround for cache flush problems. First send a dummy EOP
+	 * event down the pipe with seq one below.
+	 */
+	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
+	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
+				 EOP_TC_ACTION_EN |
+				 EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+				 EVENT_INDEX(5)));
+	radeon_ring_write(ring, addr & 0xfffffffc);
+	radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
+				DATA_SEL(1) | INT_SEL(0));
+	radeon_ring_write(ring, fence->seq - 1);
+	radeon_ring_write(ring, 0);
+
+	/* Then send the real EOP event down the pipe. */
 	radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
 	radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
 				 EOP_TC_ACTION_EN |