[12/12] drm/i915: Enable the maxfifo PM5 mode when appropriate on CHV
diff mbox

Message ID 1423574909-1074-13-git-send-email-ville.syrjala@linux.intel.com
State New, archived
Headers show

Commit Message

Ville Syrjälä Feb. 10, 2015, 1:28 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

CHV has a new knob in Punit to select between some memory power savings
modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
enabled, so let's do so in the hopes for moar power savings.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

Comments

Shuang He Feb. 11, 2015, 12:01 a.m. UTC | #1
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 5748
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV              +3                 275/283              278/283
ILK              +1-2              310/315              309/315
SNB              +3                 320/346              323/346
IVB                 -1              380/384              379/384
BYT                                  296/296              296/296
HSW              +3                 422/428              425/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
 PNV  igt_gem_userptr_blits_coherency-sync      CRASH(3, M7)PASS(2, M7)      PASS(1, M7)
 PNV  igt_gem_userptr_blits_coherency-unsync      CRASH(3, M7)PASS(3, M7)      PASS(1, M7)
 PNV  igt_gem_userptr_blits_create-destroy-sync      NRUN(1, M7)PASS(5, M7)      PASS(1, M7)
 PNV  igt_gen3_render_tiledx_blits      FAIL(2, M7)TIMEOUT(1, M7)PASS(3, M7)      FAIL(1, M7)
 ILK  igt_gem_fenced_exec_thrash_no-spare-fences-busy-interruptible      DMESG_WARN(1, M26)PASS(1, M26)      DMESG_WARN(1, M26)
*ILK  igt_gem_unfence_active_buffers      PASS(3, M26)      DMESG_WARN(1, M26)
*ILK  igt_drv_suspend_forcewake      DMESG_WARN(3, M26)      PASS(1, M26)
*SNB  igt_kms_flip_bo-too-big      BLACKLIST(1, M35)      PASS(1, M35)
*SNB  igt_kms_flip_bo-too-big-interruptible      BLACKLIST(1, M35)      PASS(1, M35)
*SNB  igt_kms_flip_event_leak      NSPT(5, M35)      PASS(1, M35)
 IVB  igt_gem_storedw_batches_loop_normal      DMESG_WARN(1, M4)PASS(4, M4)      DMESG_WARN(1, M4)
*HSW  igt_kms_flip_bo-too-big      BLACKLIST(1, M40)      PASS(1, M40)
*HSW  igt_kms_flip_bo-too-big-interruptible      BLACKLIST(1, M40)      PASS(1, M40)
 HSW  igt_kms_flip_plain-flip-fb-recreate-interruptible      TIMEOUT(5, M40)PASS(2, M40)      PASS(1, M40)
Note: You need to pay more attention to line start with '*'
Vijay Purushothaman March 4, 2015, 2:28 p.m. UTC | #2
On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> CHV has a new knob in Punit to select between some memory power savings
> modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
> enabled, so let's do so in the hopes for moar power savings.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/i915_reg.h |  3 +++
>   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
>   2 files changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a0a7688..2196e57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -552,6 +552,9 @@
>   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
>   #define   DSPFREQGUAR_SHIFT			14
>   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
>   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
>   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
>   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index e6cbc24..4e11552 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
>   	struct drm_device *dev = dev_priv->dev;
>   	u32 val;
>   
> -	if (IS_VALLEYVIEW(dev)) {
> +	if (IS_CHERRYVIEW(dev)) {
> +		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> +
> +		mutex_lock(&dev_priv->rps.hw_lock);
> +		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> +		if (enable)
> +			val |= DSP_MAXFIFO_PM5_ENABLE;
> +		else
> +			val &= ~DSP_MAXFIFO_PM5_ENABLE;
> +		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> +		mutex_unlock(&dev_priv->rps.hw_lock);
> +	} else if (IS_VALLEYVIEW(dev)) {
>   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
>   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
>   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
Since you are enabling MaxFIFO for multi plane in one of the previous 
patches, i guess PM5 will also be enabled when more than one plane is 
active in this flow.
Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
is the only validated scenario by SV.

With this addressed,
Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>

Thanks,
Vijay
Ville Syrjälä March 4, 2015, 3:07 p.m. UTC | #3
On Wed, Mar 04, 2015 at 07:58:50PM +0530, Purushothaman, Vijay A wrote:
> On 2/10/2015 6:58 PM, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > CHV has a new knob in Punit to select between some memory power savings
> > modes PM2 and PM5. We can allow the deeper PM5 when maxfifo mode is
> > enabled, so let's do so in the hopes for moar power savings.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/i915_reg.h |  3 +++
> >   drivers/gpu/drm/i915/intel_pm.c | 13 ++++++++++++-
> >   2 files changed, 15 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index a0a7688..2196e57 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -552,6 +552,9 @@
> >   #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
> >   #define   DSPFREQGUAR_SHIFT			14
> >   #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
> > +#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
> > +#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
> > +#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
> >   #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
> >   #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
> >   #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index e6cbc24..4e11552 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -240,7 +240,18 @@ void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
> >   	struct drm_device *dev = dev_priv->dev;
> >   	u32 val;
> >   
> > -	if (IS_VALLEYVIEW(dev)) {
> > +	if (IS_CHERRYVIEW(dev)) {
> > +		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> > +
> > +		mutex_lock(&dev_priv->rps.hw_lock);
> > +		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
> > +		if (enable)
> > +			val |= DSP_MAXFIFO_PM5_ENABLE;
> > +		else
> > +			val &= ~DSP_MAXFIFO_PM5_ENABLE;
> > +		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
> > +		mutex_unlock(&dev_priv->rps.hw_lock);
> > +	} else if (IS_VALLEYVIEW(dev)) {
> >   		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
> >   	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
> >   		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
> Since you are enabling MaxFIFO for multi plane in one of the previous 
> patches, i guess PM5 will also be enabled when more than one plane is 
> active in this flow.
> Let's enable MaxFIFO and PM5 when only one plane is active for now. This 
> is the only validated scenario by SV.

Yep that's good enough for me.

> 
> With this addressed,
> Reviewed-by: Vijay Purushothaman <vijay.a.purushothaman@linux.intel.com>
> 
> Thanks,
> Vijay
> 
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a0a7688..2196e57 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -552,6 +552,9 @@ 
 #define   DSPFREQSTAT_MASK			(0x3 << DSPFREQSTAT_SHIFT)
 #define   DSPFREQGUAR_SHIFT			14
 #define   DSPFREQGUAR_MASK			(0x3 << DSPFREQGUAR_SHIFT)
+#define   DSP_MAXFIFO_PM5_STATUS		(1 << 22) /* chv */
+#define   DSP_AUTO_CDCLK_GATE_DISABLE		(1 << 7) /* chv */
+#define   DSP_MAXFIFO_PM5_ENABLE		(1 << 6) /* chv */
 #define   _DP_SSC(val, pipe)			((val) << (2 * (pipe)))
 #define   DP_SSC_MASK(pipe)			_DP_SSC(0x3, (pipe))
 #define   DP_SSC_PWR_ON(pipe)			_DP_SSC(0x0, (pipe))
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e6cbc24..4e11552 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -240,7 +240,18 @@  void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 	struct drm_device *dev = dev_priv->dev;
 	u32 val;
 
-	if (IS_VALLEYVIEW(dev)) {
+	if (IS_CHERRYVIEW(dev)) {
+		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
+
+		mutex_lock(&dev_priv->rps.hw_lock);
+		val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
+		if (enable)
+			val |= DSP_MAXFIFO_PM5_ENABLE;
+		else
+			val &= ~DSP_MAXFIFO_PM5_ENABLE;
+		vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
+		mutex_unlock(&dev_priv->rps.hw_lock);
+	} else if (IS_VALLEYVIEW(dev)) {
 		I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 	} else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 		I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);