From patchwork Fri Mar 11 20:47:23 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zou, Nanhai" X-Patchwork-Id: 629171 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id p2BKoBSN014656 for ; Fri, 11 Mar 2011 20:50:32 GMT Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 162FC9EFCD for ; Fri, 11 Mar 2011 12:50:11 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 2EFAD9E747 for ; Fri, 11 Mar 2011 12:49:48 -0800 (PST) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP; 11 Mar 2011 12:49:47 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.62,305,1297065600"; d="scan'208";a="611965736" Received: from pgsmsx601.gar.corp.intel.com ([10.221.43.69]) by orsmga002.jf.intel.com with ESMTP; 11 Mar 2011 12:49:41 -0800 Received: from shsmsx601.ccr.corp.intel.com (10.239.4.112) by pgsmsx601.gar.corp.intel.com (10.221.43.69) with Microsoft SMTP Server (TLS) id 8.2.254.0; Sat, 12 Mar 2011 04:49:40 +0800 Received: from shsmsx502.ccr.corp.intel.com ([10.239.4.96]) by shsmsx601.ccr.corp.intel.com ([10.239.4.112]) with mapi; Sat, 12 Mar 2011 04:49:39 +0800 From: "Zou, Nanhai" To: Eric Anholt , "intel-gfx@lists.freedesktop.org" Date: Sat, 12 Mar 2011 04:47:23 +0800 Thread-Topic: [Intel-gfx] [PATCH] drm/i915: Use the LLC mode on gen6 for everything but display. Thread-Index: AcvgKI+GNhd8jZzGTWqCceAPFWFFFgABPaRW Message-ID: <41EFD7A46E18724CAB128DAD0073348019F8475553@shsmsx502.ccr.corp.intel.com> References: <1299874280-2288-1-git-send-email-eric@anholt.net> In-Reply-To: <1299874280-2288-1-git-send-email-eric@anholt.net> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: acceptlanguage: en-US MIME-Version: 1.0 Subject: Re: [Intel-gfx] [PATCH] drm/i915: Use the LLC mode on gen6 for everything but display. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.11 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.6 (demeter1.kernel.org [140.211.167.41]); Fri, 11 Mar 2011 20:50:32 +0000 (UTC) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 36e66cc..f4f6de3 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -3539,7 +3539,23 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, obj->base.write_domain = I915_GEM_DOMAIN_CPU; obj->base.read_domains = I915_GEM_DOMAIN_CPU; - obj->agp_type = AGP_USER_MEMORY; + if (IS_GEN6(dev)) { + /* On Gen6, we can have the GPU use the LLC (the CPU + * cache) for about a 10% performance improvement + * compared to uncached. Graphics requests other than + * display scanout are coherent with the CPU in + * accessing this cache. This means in this mode we + * don't need to clflush on the CPU side, and on the + * GPU side we only need to flush internal caches to + * get data visible to the CPU. + * + * For display, see intel_pin_and_fence_fb_obj() for + * how we handle changing the caching. + */ + obj->agp_type = AGP_USER_CACHED_MEMORY; + } else { + obj->agp_type = AGP_USER_MEMORY; + } obj->base.driver_private = NULL; obj->fence_reg = I915_FENCE_REG_NONE; INIT_LIST_HEAD(&obj->mm_list); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 49fb54f..0b3096a 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1456,6 +1456,45 @@ out_disable: } } +/* The display engine is not coherent with the LLC cache on gen6. As + * a result, we make sure that the pinning that is about to occur is + * done with uncached PTEs. + * + * We could do this better in a couple of ways. The most important + * would be to use the GFDT bit instead of uncaching, which would + * allow us to flush all the LLC-cached data with that bit in the PTE + * to main memory with just one PIPE_CONTROL. The other would be to + * update the PTEs by calling i915_gem_gtt_bind_object() and then + * flush any existing CPU cache of the object, instead of unbinding. + */ +static int +i915_set_pte_uncached(struct drm_i915_gem_object *obj) +{ + int ret; + + if (obj->agp_type == AGP_USER_MEMORY) + return 0; + + obj->agp_type = AGP_USER_MEMORY; + + if (obj->pin_count > 0) { + static int once = 0; + if (!once) { + DRM_ERROR("Trying to change caching on pinned fb\n"); + once = 1; + } + return -EBUSY; + } + + ret = i915_gem_object_unbind(obj); + if (ret) + return ret; + + obj->agp_type = AGP_USER_MEMORY; + + return 0; +} + int intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_i915_gem_object *obj, @@ -1485,6 +1524,12 @@ intel_pin_and_fence_fb_obj(struct drm_device *dev, BUG(); } + if (IS_GEN6(dev)) { + ret = i915_set_pte_uncached(obj); + if (ret) + return ret; + } + ret = i915_gem_object_pin(obj, alignment, true); if (ret) return ret; @@ -4740,6 +4785,12 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc, goto fail_locked; } + if (IS_GEN6(dev)) { + ret = i915_set_pte_uncached(obj); + if (ret) + goto fail_locked; + } + ret = i915_gem_object_pin(obj, PAGE_SIZE, true); if (ret) { DRM_ERROR("failed to pin cursor bo\n");