[4/6] intel: Keep the caches in loose active order
diff mbox

Message ID 1430816040-25285-4-git-send-email-chris@chris-wilson.co.uk
State New
Headers show

Commit Message

Chris Wilson May 5, 2015, 8:53 a.m. UTC
Though we don't have precise tracking for when buffers in the cache list
become idle (we don't have request tracking at this layer), we do have
some basic assumptions that the head is inactive and the tail active. So
when inserting buffers in the cache, it would be good not to completely
ignore those assumptions.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
 intel/intel_bufmgr_gem.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff mbox

diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 61a248f..2cbe973 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -1329,7 +1329,10 @@  drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time)
 		bo_gem->name = NULL;
 		bo_gem->validate_index = -1;
-		DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
+		if (drm_intel_gem_bo_busy(&bo_gem->bo))
+			DRMLISTADDTAIL(&bo_gem->head, &bucket->head);
+		else
+			DRMLISTADD(&bo_gem->head, &bucket->head);
 	} else {