[07/12] drm/i915: Write the SDVO reg twice on IBX
diff mbox

Message ID 1430835458-11187-8-git-send-email-ville.syrjala@linux.intel.com
State New
Headers show

Commit Message

Ville Syrjälä May 5, 2015, 2:17 p.m. UTC
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On IBX the SDVO/HDMI register write may be masked when enabling the
port, so it may need to written twice. The HDMI code does this, but
the SDVO code does not. Add the workaround to the SDVO code as well.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++
 1 file changed, 8 insertions(+)

Comments

Jesse Barnes May 21, 2015, 7:20 p.m. UTC | #1
On 05/05/2015 07:17 AM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> On IBX the SDVO/HDMI register write may be masked when enabling the
> port, so it may need to written twice. The HDMI code does this, but
> the SDVO code does not. Add the workaround to the SDVO code as well.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
> index 0a06257..e3e9c98 100644
> --- a/drivers/gpu/drm/i915/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/intel_sdvo.c
> @@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
>  	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
>  		I915_WRITE(intel_sdvo->sdvo_reg, val);
>  		POSTING_READ(intel_sdvo->sdvo_reg);
> +		/*
> +		 * HW workaround, need to write this twice for issue
> +		 * that may result in first write getting masked.
> +		 */
> +		if (HAS_PCH_IBX(dev)) {
> +			I915_WRITE(intel_sdvo->sdvo_reg, val);
> +			POSTING_READ(intel_sdvo->sdvo_reg);
> +		}
>  		return;
>  	}
>  
> 

This must be the missing fix to all our SDVO problems.  (One can hope.)

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 0a06257..e3e9c98 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -243,6 +243,14 @@  static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
 	if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
 		I915_WRITE(intel_sdvo->sdvo_reg, val);
 		POSTING_READ(intel_sdvo->sdvo_reg);
+		/*
+		 * HW workaround, need to write this twice for issue
+		 * that may result in first write getting masked.
+		 */
+		if (HAS_PCH_IBX(dev)) {
+			I915_WRITE(intel_sdvo->sdvo_reg, val);
+			POSTING_READ(intel_sdvo->sdvo_reg);
+		}
 		return;
 	}