drm/i915/skl: Fix FF_SLICE_CS_CHICKEN2 offset
diff mbox

Message ID 1430917490-29186-1-git-send-email-damien.lespiau@intel.com
State New
Headers show

Commit Message

Lespiau, Damien May 6, 2015, 1:04 p.m. UTC
Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.

The problem was introduced in the original patch:

  commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
  Author: Damien Lespiau <damien.lespiau@intel.com>
  Date:   Mon Feb 9 19:33:20 2015 +0000

      drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS

Reported-by: Robert Beckett <robert.beckett@intel.com>
Cc: Robert Beckett <robert.beckett@intel.com>
Cc: Nick Hoath <nicholas.hoath@intel.com>

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ville Syrjälä May 6, 2015, 1:20 p.m. UTC | #1
On Wed, May 06, 2015 at 02:04:50PM +0100, Damien Lespiau wrote:
> Robert noticed that the FF_SLICE_CS_CHICKEN2 offset was wrong. Ooops.
> 
> The problem was introduced in the original patch:
> 
>   commit 2caa3b260aa6a3d015352c07d1bce1461825fa6c
>   Author: Damien Lespiau <damien.lespiau@intel.com>
>   Date:   Mon Feb 9 19:33:20 2015 +0000
> 
>       drm/i915/skl: Implement WaDisableChickenBitTSGBarrierAckForFFSliceCS
> 
> Reported-by: Robert Beckett <robert.beckett@intel.com>
> Cc: Robert Beckett <robert.beckett@intel.com>
> Cc: Nick Hoath <nicholas.hoath@intel.com>
> 
> Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>

FYI the code in skl_init_clock_gating() is also wrong since this is
a masked register.

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5436ab0..6a1875a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5718,7 +5718,7 @@ enum skl_disp_power_wells {
>  #define HSW_NDE_RSTWRN_OPT	0x46408
>  #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
>  
> -#define FF_SLICE_CS_CHICKEN2			0x02e4
> +#define FF_SLICE_CS_CHICKEN2			0x20e4
>  #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
>  
>  /* GEN7 chicken */
> -- 
> 2.1.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
Shuang He May 7, 2015, 1:27 p.m. UTC | #2
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6331
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  302/302              302/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
Note: You need to pay more attention to line start with '*'

Patch
diff mbox

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5436ab0..6a1875a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5718,7 +5718,7 @@  enum skl_disp_power_wells {
 #define HSW_NDE_RSTWRN_OPT	0x46408
 #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
 
-#define FF_SLICE_CS_CHICKEN2			0x02e4
+#define FF_SLICE_CS_CHICKEN2			0x20e4
 #define  GEN9_TSG_BARRIER_ACK_DISABLE		(1<<8)
 
 /* GEN7 chicken */