diff mbox

[v2,2/2] drm/i915/chv: Extend set idle rps wa to chv

Message ID 1431097992-18204-2-git-send-email-deepak.s@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

deepak.s@linux.intel.com May 8, 2015, 3:13 p.m. UTC 
From: Deepak S <deepak.s@linux.intel.com>

It is obsered on BSW that requesting a new frequency from Punit
does nothing when the GPU is in rc6, and if we let it enter rc6 with a
high frequency Vnn also remains high. Extending vlv_set_rps_idle()
workaround on CHV/BSW.

suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Deepak S <deepak.s@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 7 -------
 1 file changed, 7 deletions(-)

Comments

Ville Syrjälä May 8, 2015, 4:36 p.m. UTC | #1 
On Fri, May 08, 2015 at 08:43:11PM +0530, deepak.s@linux.intel.com wrote:
> From: Deepak S <deepak.s@linux.intel.com>
> 
> It is obsered on BSW that requesting a new frequency from Punit
> does nothing when the GPU is in rc6, and if we let it enter rc6 with a
> high frequency Vnn also remains high.

I would perhaps rephrase that as "slightly higher than at the
minimum frequency" since it does drop most of the way, at least on
my BSW.

Otherwise this is
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> Extending vlv_set_rps_idle()
> workaround on CHV/BSW.
> 
> suggested-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Deepak S <deepak.s@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 3df929a..852f756 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4052,15 +4052,8 @@ static void valleyview_set_rps(struct drm_device *dev, u8 val)
>  */
>  static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_device *dev = dev_priv->dev;
>  	u32 val = dev_priv->rps.idle_freq;
>  
> -	/* CHV don't need to force the gfx clock */
> -	if (IS_CHERRYVIEW(dev)) {
> -		valleyview_set_rps(dev_priv->dev, val);
> -		return;
> -	}
> -
>  	if (dev_priv->rps.cur_freq <= val)
>  		return;
>  
> -- 
> 1.9.1
Shuang He May 9, 2015, 10:32 a.m. UTC | #2 
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6362
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                 -1              302/302              301/302
SNB                                  316/316              316/316
IVB                                  342/342              342/342
BYT                                  286/286              286/286
BDW                                  321/321              321/321
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series Applied
*ILK  igt@drv_suspend@fence-restore-tiled2untiled      PASS(2)      DMESG_WARN(1)PASS(1)
(dmesg patch applied)drm:drm_edid_block_valid[drm]]*ERROR*EDID_checksum_is_invalid,remainder_is@EDID checksum is .* remainder is
Note: You need to pay more attention to line start with '*'
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3df929a..852f756 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4052,15 +4052,8 @@  static void valleyview_set_rps(struct drm_device *dev, u8 val)
 */
 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
 {
-	struct drm_device *dev = dev_priv->dev;
 	u32 val = dev_priv->rps.idle_freq;
 
-	/* CHV don't need to force the gfx clock */
-	if (IS_CHERRYVIEW(dev)) {
-		valleyview_set_rps(dev_priv->dev, val);
-		return;
-	}
-
 	if (dev_priv->rps.cur_freq <= val)
 		return;