From patchwork Mon May 11 18:19:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 6381031 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 248AB9F399 for ; Mon, 11 May 2015 18:20:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 4368C20A32 for ; Mon, 11 May 2015 18:20:09 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 3BB6D20A2B for ; Mon, 11 May 2015 18:20:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C36096E4B5; Mon, 11 May 2015 11:20:06 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B39B6E4A7 for ; Mon, 11 May 2015 11:20:04 -0700 (PDT) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP; 11 May 2015 11:20:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,409,1427785200"; d="scan'208";a="693209129" Received: from unknown (HELO rdvivi-talin.jf.intel.com) ([10.7.196.74]) by orsmga001.jf.intel.com with ESMTP; 11 May 2015 11:20:04 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Mon, 11 May 2015 11:19:56 -0700 Message-Id: <1431368400-1942-5-git-send-email-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.1.0 In-Reply-To: <1431368400-1942-1-git-send-email-rodrigo.vivi@intel.com> References: <1431368400-1942-1-git-send-email-rodrigo.vivi@intel.com> Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 4/8] drm/i915: Changes required to enable DSI Video Mode on CHT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Gaurav K Singh On CHT, changes are required for calculating the correct m,n & p with minimal error +/- for the required DSI clock, so that the correct dividor & ctrl values are written in cck regs for DSI. This patch has been tested on CHT RVP with 1200 x 1920 panel. Signed-off-by: Gaurav K Singh Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_dsi_pll.c | 43 +++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index 471336d..5e44c9b 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c @@ -162,7 +162,8 @@ static u32 dsi_clk_from_pclk(u32 pclk, int pixel_format, int lane_count) #endif -static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) +static int dsi_calc_mnp(struct drm_i915_private *dev_priv, + u32 dsi_clk, struct dsi_mnp *dsi_mnp) { u32 m, n, p; u32 ref_clk; @@ -173,6 +174,10 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) u32 calc_m; u32 calc_p; u32 m_seed; + u32 m_start; + u32 m_limit; + u32 n_limit; + u32 p_limit; /* dsi_clk is expected in KHZ */ if (dsi_clk < 300000 || dsi_clk > 1150000) { @@ -180,18 +185,33 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) return -ECHRNG; } - ref_clk = 25000; + if (IS_CHERRYVIEW(dev_priv->dev)) { + ref_clk = 100000; + m_start = 70; + m_limit = 96; + n_limit = 4; + p_limit = 6; + } else if (IS_VALLEYVIEW(dev_priv->dev)) { + ref_clk = 25000; + m_start = 62; + m_limit = 92; + n_limit = 1; + p_limit = 6; + } else { + DRM_ERROR("Unsupported device\n"); + return -ENODEV; + } target_dsi_clk = dsi_clk; error = 0xFFFFFFFF; tmp_error = 0xFFFFFFFF; calc_m = 0; calc_p = 0; - for (m = 62; m <= 92; m++) { - for (p = 2; p <= 6; p++) { + for (m = m_start; m <= m_limit; m++) { + for (p = 2; p <= p_limit; p++) { /* Find the optimal m and p divisors with minimal error +/- the required clock */ - calc_dsi_clk = (m * ref_clk) / p; + calc_dsi_clk = (m * ref_clk) / (p * n_limit); if (calc_dsi_clk == target_dsi_clk) { calc_m = m; calc_p = p; @@ -212,11 +232,14 @@ static int dsi_calc_mnp(u32 dsi_clk, struct dsi_mnp *dsi_mnp) } m_seed = lfsr_converts[calc_m - 62]; - n = 1; + n = n_limit; dsi_mnp->dsi_pll_ctrl = 1 << (DSI_PLL_P1_POST_DIV_SHIFT + calc_p - 2); - dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | - m_seed << DSI_PLL_M1_DIV_SHIFT; - + if (IS_CHERRYVIEW(dev_priv->dev)) + dsi_mnp->dsi_pll_div = (n/2) << DSI_PLL_N1_DIV_SHIFT | + m_seed << DSI_PLL_M1_DIV_SHIFT; + else + dsi_mnp->dsi_pll_div = (n - 1) << DSI_PLL_N1_DIV_SHIFT | + m_seed << DSI_PLL_M1_DIV_SHIFT; return 0; } @@ -235,7 +258,7 @@ static void vlv_configure_dsi_pll(struct intel_encoder *encoder) dsi_clk = dsi_clk_from_pclk(intel_dsi->pclk, intel_dsi->pixel_format, intel_dsi->lane_count); - ret = dsi_calc_mnp(dsi_clk, &dsi_mnp); + ret = dsi_calc_mnp(dev_priv, dsi_clk, &dsi_mnp); if (ret) { DRM_DEBUG_KMS("dsi_calc_mnp failed\n"); return;