From patchwork Wed May 13 06:50:35 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: vandana.kannan@intel.com X-Patchwork-Id: 6393881 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 0545CBEEE1 for ; Wed, 13 May 2015 06:27:17 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2D3AF20426 for ; Wed, 13 May 2015 06:27:16 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 327C42041E for ; Wed, 13 May 2015 06:27:15 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 667146E6F2; Tue, 12 May 2015 23:27:14 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 9D4236E6F2 for ; Tue, 12 May 2015 23:27:13 -0700 (PDT) Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP; 12 May 2015 23:27:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.13,419,1427785200"; d="scan'208";a="728343285" Received: from vkannan-desktop.iind.intel.com ([10.223.25.137]) by orsmga002.jf.intel.com with ESMTP; 12 May 2015 23:27:12 -0700 From: Vandana Kannan To: intel-gfx@lists.freedesktop.org Date: Wed, 13 May 2015 12:20:35 +0530 Message-Id: <1431499835-24704-1-git-send-email-vandana.kannan@intel.com> X-Mailer: git-send-email 2.0.1 In-Reply-To: <1431004070.8610.20.camel@intel.com> References: <1431004070.8610.20.camel@intel.com> Subject: [Intel-gfx] [PATCH v2 2/2] drm/i915/bxt: Move around lane stagger calculation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Making lane stagger calculation common for HDMI and DP v2: Imre's comments addressed - Remove lane stagger from bxt_clk_div and make it a local variable in ddi_pll_select Signed-off-by: Vandana Kannan Reviewed-by: Imre Deak --- drivers/gpu/drm/i915/intel_ddi.c | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index a56613c..aadd29e 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1333,18 +1333,17 @@ struct bxt_clk_div { uint32_t m2_frac; bool m2_frac_en; uint32_t n; - uint32_t lanestagger; }; /* pre-calculated values for DP linkrates */ static struct bxt_clk_div bxt_dp_clk_val[7] = { - /* 162 */ {4, 2, 32, 1677722, 1, 1, 0xd}, - /* 270 */ {4, 1, 27, 0, 0, 1, 0xd}, - /* 540 */ {2, 1, 27, 0, 0, 1, 0x18}, - /* 216 */ {3, 2, 32, 1677722, 1, 1, 0xd}, - /* 243 */ {4, 1, 24, 1258291, 1, 1, 0xd}, - /* 324 */ {4, 1, 32, 1677722, 1, 1, 0x18}, - /* 432 */ {3, 1, 32, 1677722, 1, 1, 0x18} + /* 162 */ {4, 2, 32, 1677722, 1, 1}, + /* 270 */ {4, 1, 27, 0, 0, 1}, + /* 540 */ {2, 1, 27, 0, 0, 1}, + /* 216 */ {3, 2, 32, 1677722, 1, 1}, + /* 243 */ {4, 1, 24, 1258291, 1, 1}, + /* 324 */ {4, 1, 32, 1677722, 1, 1}, + /* 432 */ {3, 1, 32, 1677722, 1, 1} }; static bool @@ -1357,7 +1356,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, struct bxt_clk_div clk_div = {0}; int vco = 0; uint32_t prop_coef, int_coef, gain_ctl, targ_cnt; - uint32_t dcoampovr_en_h, dco_amp; + uint32_t dcoampovr_en_h, dco_amp, lanestagger; if (intel_encoder->type == INTEL_OUTPUT_HDMI) { intel_clock_t best_clock; @@ -1382,16 +1381,6 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, clk_div.m2_frac_en = clk_div.m2_frac != 0; vco = best_clock.vco; - if (clock > 270000) - clk_div.lanestagger = 0x18; - else if (clock > 135000) - clk_div.lanestagger = 0x0d; - else if (clock > 67000) - clk_div.lanestagger = 0x07; - else if (clock > 33000) - clk_div.lanestagger = 0x04; - else - clk_div.lanestagger = 0x02; } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || intel_encoder->type == INTEL_OUTPUT_EDP) { struct drm_encoder *encoder = &intel_encoder->base; @@ -1439,6 +1428,17 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, return false; } + if (clock > 270000) + lanestagger = 0x18; + else if (clock > 135000) + lanestagger = 0x0d; + else if (clock > 67000) + lanestagger = 0x07; + else if (clock > 33000) + lanestagger = 0x04; + else + lanestagger = 0x02; + crtc_state->dpll_hw_state.ebb0 = PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; @@ -1462,7 +1462,7 @@ bxt_ddi_pll_select(struct intel_crtc *intel_crtc, crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp); crtc_state->dpll_hw_state.pcsdw12 = - LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; + LANESTAGGER_STRAP_OVRD | lanestagger; pll = intel_get_shared_dpll(intel_crtc, crtc_state); if (pll == NULL) {