From patchwork Sat May 16 04:45:51 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhichao Huang X-Patchwork-Id: 6419041 Return-Path: X-Original-To: patchwork-kvm@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 53C779F1C1 for ; Sat, 16 May 2015 04:47:31 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 76DF0203AA for ; Sat, 16 May 2015 04:47:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8FE6120204 for ; Sat, 16 May 2015 04:47:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1422905AbbEPEr0 (ORCPT ); Sat, 16 May 2015 00:47:26 -0400 Received: from mail-pd0-f174.google.com ([209.85.192.174]:32936 "EHLO mail-pd0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1030224AbbEPErX (ORCPT ); Sat, 16 May 2015 00:47:23 -0400 Received: by pdbqa5 with SMTP id qa5so46351232pdb.0 for ; Fri, 15 May 2015 21:47:23 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vaCRIyMvD6CM/vZlsiUB4optrMws1E4tgLW2nKCre+Y=; b=Fp4M75z7xGKkTuw0dHJPAy0RER4SnG6kDCZU88lpAzgGLmCQn4spIoLgjcvsUT1/C8 pYZovC/dfRlFE0THrQdy5GtDTw+hp3sRT9Drd5VujZMplRVo4BizBZODqKFpi0ycDi7P S4/RkWR538v3rf0x+ACHOxR7yXe7SX/97/iDd8QhrMCBfBmChDS1rWdp+9sDKOoQQtKK YNp4qh2Jpu2G7qt/OCJjeGaU7CAIwcEJguu6Itl3dqnWxrHqkPy0fb687+U5tAoAICCV ad4Y3fN3gcfFbc9kYGascXitLiERaeimKeELQBmzJSArkwO6j+VdbH3bkZbN4wx1dRst TFLA== X-Gm-Message-State: ALoCoQkKh+A9Tpxm6WharZVFyWdWUut3X7R8CHgdQBHygwwFftRY5HF1X2/518Msp/j8jbLenows X-Received: by 10.68.219.201 with SMTP id pq9mr24560425pbc.97.1431751643547; Fri, 15 May 2015 21:47:23 -0700 (PDT) Received: from localhost ([167.160.116.91]) by mx.google.com with ESMTPSA id v3sm3377758pbs.18.2015.05.15.21.47.20 (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 15 May 2015 21:47:22 -0700 (PDT) From: Zhichao Huang To: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, christoffer.dall@linaro.org, marc.zyngier@arm.com, alex.bennee@linaro.org Cc: huangzhichao@huawei.com, Zhichao Huang Subject: [PATCH 10/10] KVM: arm: enable trapping of all debug registers Date: Sat, 16 May 2015 12:45:51 +0800 Message-Id: <1431751551-4788-11-git-send-email-zhichao.huang@linaro.org> X-Mailer: git-send-email 1.9.5.msysgit.1 In-Reply-To: <1431751551-4788-1-git-send-email-zhichao.huang@linaro.org> References: <1431751551-4788-1-git-send-email-zhichao.huang@linaro.org> Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable trapping of the debug registers, allowing guests to use the debug infrastructure. Signed-off-by: Zhichao Huang --- arch/arm/kvm/interrupts_head.S | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm/kvm/interrupts_head.S b/arch/arm/kvm/interrupts_head.S index ed406be..107bda4 100644 --- a/arch/arm/kvm/interrupts_head.S +++ b/arch/arm/kvm/interrupts_head.S @@ -886,10 +886,21 @@ ARM_BE8(rev r6, r6 ) .endm /* Configures the HDCR (Hyp Debug Configuration Register) on entry/return - * (hardware reset value is 0) */ + * (hardware reset value is 0) + * + * Clobbers r2-r4 + */ .macro set_hdcr operation mrc p15, 4, r2, c1, c1, 1 - ldr r3, =(HDCR_TPM|HDCR_TPMCR) + ldr r3, =(HDCR_TPM|HDCR_TPMCR|HDCR_TDRA|HDCR_TDOSA) + + // Check for KVM_ARM_DEBUG_DIRTY, and set debug to trap + // if not dirty. + ldr r4, [vcpu, #VCPU_DEBUG_FLAGS] + cmp r4, #KVM_ARM_DEBUG_DIRTY + beq 1f + orr r3, r3, #HDCR_TDA +1: .if \operation == vmentry orr r2, r2, r3 @ Trap some perfmon accesses .else